Data Sheet

AD7265

Rev. B | Page 7 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

24 A1

23 A2

22 SGL/DIFF

21 RANGE

19 AGND

1

2

3

4

5

6

7

8

DGND

REF SELECT

AGND

AGND

AD7265

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE PACK

CONNECT THE EPAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS

Figure 2. 32-Lead CP-32-7

SGL/DIFF

1

2

3

4

5

6

7

8

REF SELECT

AGND

AGND

DGND

23

A2

22

21

RANGE

18

19

AGND

20

24

A1

17

PIN 1

9

10 11

12

13 14 15

16

32 31 30

29 28 27 26

25

AD7265

TOP VIEW

(Not to Scale)

Figure 3. 32-Lead SU-32-2

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 29

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

2

REF SELECT

Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used

decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the

3

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The

transient basis. This supply should be decoupled to AGND.

4, 20

Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to

decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference

can be taken from these pins and applied externally to the rest of a system. The range of the external reference is

dependent on the analog input range selected.

5, 6, 19

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any

external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect

to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must

not be more than 0.3 V apart, even on a transient basis.

7 to 12

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential

analog input channel pairs. See Table 6.

13 to 18

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential

analog input channel pairs. See Table 6.

21

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog

22

SGL/DIFF

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A

logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input

Selection section for details.

23 to 25

A2 to A0

Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously

converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair

of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins

need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the

multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for

multiplexer address decoding.

26

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265

and framing the serial data transfer.