Timing Diagrams

TLDD6919 – 4

FIGURE 3 InputOutput Timing Diagrams (Ceramic Resonator Divide-by-8 Mode)

TLDD6919 – 5

FIGURE 3a Synchronization Timing

Functional Description

A block diagram of the COP410L is given in

Figure 1 Data

paths are illustrated in simplified form to depict how the vari-

ous logic elements communicate with each other in imple-

menting the instruction set of the device Positive logic is

used When a bit is set it is a logic ‘‘1’’ (greater than 2V)

When a bit is reset it is a logic ‘‘0’’ (less than 08V)

All functional references to the COP410LCOP411L also

apply to the COP310LCOP311L

PROGRAM MEMORY

Program Memory consists of a 512-byte ROM As can be

seen by an examination of the COP410L411L instruction

set these words may be program instructions program data

or ROM addressing data Because of the special character-

istics associated with the JP JSRP JID and LQID instruc-

tions ROM must often be thought of as being organized into

8 pages of 64 words each

ROM addressing is accomplished by a 9-bit PC register Its

binary value selects one of the 512 8-bit words contained in

ROM A new address is loaded into the PC register during

each instruction cycle Unless the instruction is a transfer of

control instruction the PC register is loaded with the next

sequential 9-bit binary count value Two levels of subroutine

nesting are implemented by the 9-bit subroutine save regis-

ters SA and SB providing a last-in first-out (LIFO) hard-

ware subroutine stack

ROM instruction words are fetched decoded and executed

by the Instruction Decode Control and Skip Logic circuitry

DATA MEMORY

Data memory consists of a 128-bit RAM organized as 4

data registers of 8 4-bit digits RAM addressing is imple-

mented by a 6-bit B register whose upper 2 bits (Br) select 1

of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of

8 4-bit digits in the selected data register While the 4-bit

contents of the selected RAM digit (M) is usually loaded into

or from or exchanged with the A register (accumulator) it

may also be loaded into the Q latches or loaded from the L

ports RAM addressing may also be performed directly by

the XAD 315 instruction The Bd register also serves as a

source register for 4-bit data sent directly to the D outputs

The most significant bit of Bd is not used to select a RAM

digit Hence each physical digit of RAM may be selected by

two different values of Bd as shown in

Figure 4 below The

skip condition for XIS and XDS instructions will be true if Bd

changes between 0 and 15 but NOT between 7 and 8 (see

Table III)

Can be directly addressed by

LBI instruction (see Table III)

TLDD6919 – 6

FIGURE 4 RAM Digit Address to

Physical RAM Digit Mapping

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