COP410L datasheet(8/20 Pages) NSC

8 / 20 page

Functional Description (Continued)

INTERNAL LOGIC

The 4-bit A register (accumulator) is the source and destina-

tion register for most IO arithmetic logic and data memory

access operations It can also be used to load the Bd por-

tion of the B register to load 4 bits of the 8-bit Q latch data

to input 4 bits of the 8-bit L IO port data and to perform

data exchanges with the SIO register

A 4-bit adder performs the arithmetic and logic functions of

the COP410L411L storing its results in A It also outputs a

carry bit to the 1-bit C register most often employed to indi-

cate arithmetic overflow The C register in conjunction with

the XAS instruction and the EN register also serves to con-

trol the SK output C can be outputted directly to SK or can

enable SK to be a sync clock each instruction cycle time

(See XAS instruction and EN register description below)

The G register contents are outputs to 4 general-purpose

bidirectional IO ports

The Q register is an internal latched 8-bit register used to

hold data loaded from M and A as well as 8-bit data from

ROM Its contents are output to the L IO ports when the L

drivers are enabled under program control (See LEI instruc-

tion)

The 8 L drivers when enabled output the contents of

latched Q data to the L IO ports Also the contents of L

may be read directly into A and M L IO ports can be direct-

ly connected to the segments of a multiplexed LED display

(using the LED Direct Drive output configuration option) with

Q data being outputted to the Sa – Sg and decimal point

segments of the display

The SIO register functions as a 4-bit serial-in serial-out shift

the EN register (See EN register description below) Its

contents can be exchanged with A allowing it to input or

output a continuous serial data stream SIO may also be

used to provide additional parallel IO by connecting SO to

external serial-inparallel-out shift registers

The XAS instruction copies C into the SKL Latch In the

counter mode SK is the output of SKL in the shift register

mode SK outputs SKL ANDed with internal instruction cycle

clock

The EN register is an internal 4-bit register loaded under

program control by the LEI instruction The state of each bit

of this register selects or deselects the particular feature

associated with each bit of the EN register (EN3–EN0)

1 The least significant bit of the enable register EN0 se-

lects the SIO register as either a 4-bit shift register or a

4-bit binary counter With EN0 set SIO is an asynchro-

nous binary counter

decrementing its value by one upon

each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI

input Each pulse must be at least two instruction cycles

wide SK outputs the value of SKL The SO output is

equal to the value of EN3 With EN0 reset SIO is a serial

shift register shifting left each instruction cycle time The

data present at SI goes into the least significant bit of

SIO SO can be enabled to output the most significant bit

of SIO each cycle time (See 4 below) The SK output

becomes a logic-controlled clock

2 EN1 is not used It has no effect on COP410LCOP411L

operation

3 With EN2 set the L drivers are enabled to output the data

in Q to the L IO ports Resetting EN2 disables the L

drivers placing the L IO ports in a high-impedance input

state

4 EN3 in conjunction with EN0 affects the SO output With

EN0 set (binary counter option selected) SO will output

the value loaded into EN3 With EN0 reset (serial shift

output of the SIO shift register outputting serial shifted

data each instruction time Resetting EN3 with the serial

shift register option selected disables SO as the shift reg-

ister output data continues to be shifted through SIO and

can be exchanged with A via an XAS instruction but SO

remains reset to ‘‘0’’ Table I provides a summary of the

modes associated with EN3 and EN0

INITIALIZATION

The Reset Logic will initialize (clear) the device upon power-

up if the power supply rise time is less than 1 ms and great-

er than 1 ms If the power supply rise time is greater than

1 ms the user must provide an external RC network and

diode to the RESET pin as shown below

(Figure 5) The

RESET pin is configured as a Schmitt trigger input If not

used it should be connected to VCC Initialization will occur

whenever a logic ‘‘0’’ is applied to the RESET input provid-

ed it stays low for at least three instruction cycle times

RC t 5 c Power Supply Rise Time

TLDD6919 – 7

FIGURE 5 Power-Up Clear Circuit

TABLE I Enable Register ModesBits EN3 and EN0

EN3

EN0

SIO

Shift Register

Input to Shift Register

If SKL e 1 SK e Clock

If SKL e 0 SK e 0

Shift Register

Input to Shift Register

Serial Out

If SKL e 1 SK e Clock

If SKL e 0 SK e 0

Binary Counter

Input to Binary Counter

If SKL e 1 SK e 1

If SKL e 0 SK e 0

Binary Counter

Input to Binary Counter

If SKL e 1 SK e 1

If SKL e 0 SK e 0

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