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LTC1407/LTC1407A

1407f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX)

Maximum Sampling Frequency per Channel

1.5

MHz

(Conversion Rate)

tTHROUGHPUT

Minimum Sampling Period (Conversion + Acquisiton Period)

667

tSCK

Clock Period

(Note 16)

19.6

10000

tCONV

Conversion Time

(Note 6)

SCLK cycles

Minimum Positive or Negative SCLK Pulse Width

(Note 6)

CONV to SCK Setup Time

(Notes 6, 10)

SCK Before CONV

(Note 6)

Minimum Positive or Negative CONV Pulse Width

(Note 6)

SCK to Sample Mode

(Note 6)

CONV to Hold Mode

(Notes 6, 11)

1.2

32nd SCK

↑ to CONV↑ Interval (Affects Acquisition Period)

(Notes 6, 7, 13)

Minimum Delay from SCK to Valid Bits 0 Through 11

(Notes 6, 12)

SCK to Hi-Z at SDO

(Notes 6, 12)

t10

Previous SDO Bit Remains Valid After SCK

(Notes 6, 12)

t12

VREF Settling Time After Sleep-to-Wake Transition

(Notes 6, 14)

The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VDD

Supply Voltage

2.7

3.6

IDD

Supply Current

Active Mode, fSAMPLE = 1.5Msps

4.7

7.0

Nap Mode

1.1

1.5

Sleep Mode (LTC1407)

2.0

µA

Sleep Mode (LTC1407A)

2.0

µA

Power Dissipation

Active Mode with SCK in Fixed State (Hi or Lo)

POWER REQUIRE E TS

The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VDD = 3V.

TI I G CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground GND.

Note 3: When these pins are taken below GND or above VDD, they will be

clamped by internal diodes. This product can handle input currents greater

than 100mA below GND or greater than VDD without latchup.

Note 4: Offset and range specifications apply for a single-ended CH0+ or

CH1+ input with CH0– or CH1– grounded and using the internal 2.5V

reference.

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 8: The analog input range is defined for the voltage difference

between CH0+ and CH0– or CH1+ and CH1–.

Note 9: The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be

within this range.

Note 10: If less than 3ns is allowed, the output data will appear one clock

cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay (1ns) is the

difference between the 2.2ns delay through the sample-and-hold and the

1.2ns CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

32nd rising clock and it is ended by the rising edge of CONV.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10

µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops by 3dB with a 2.5VP-P input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock period.

Note 17: The LTC1407A is measured and specified with 14-bit Resolution

(1LSB = 152

µV) and the LTC1407 is measured and specified with 12-bit

Resolution (1LSB = 610

µV).

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