LTC1407ACMSE datasheet(7/24 Pages) LINER

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LTC1407/LTC1407A

1407f

PI FU CTIO S

CH0+ (Pin 1): Noninverting Channel 0. CH0+ operates fully

differentially with respect to CH0– with a 0V to 2.5V

differential swing and a 0 to VDD absolute input range.

CH0– (Pin 2): Inverting Channel 0. CH0– operates fully

differentially with respect to CH0+ with a –2.5V to 0V

differential swing and a 0 to VDD absolute input range.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and

a solid analog ground plane with a 10

µF ceramic capacitor

(or 10

µF tantalum in parallel with 0.1µF ceramic). Can be

overdriven by an external reference voltage

≥2.55V and

≤VDD.

CH1+ (Pin 4): Noninverting Channel 1. CH1+ operates fully

differentially with respect to CH1– with a 0V to 2.5V

differential swing and a 0 to VDD absolute input range.

CH1– (Pin 5): Inverting Channel 1. CH1– operates fully

differentially with respect to CH1+ with a –2.5V to 0V

differential swing and a 0 to VDD absolute input range.

GND (Pins 6, 11): Ground and Exposed Pad. This single

ground pin and the Exposed Pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these connections.

VDD (Pin 7): 3V Positive Supply. This single power pin

supplies 3V to the entire chip. Bypass to GND pin and solid

analog ground plane with a 10

µF ceramic capacitor (or

µF tantalum) in parallel with 0.1µF ceramic. Keep in

mind that internal analog currents and digital output signal

currents flow through this pin. Care should be taken to

place the 0.1

µF bypass capacitor as close to Pins 6 and 7

as possible.

SDO (Pin 8): Three-state Serial Data Output. Each pair of

output data words represent the two analog input chan-

nels at the start of the previous conversion.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. One or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the two analog input

signals and starts the conversion on the rising edge. Two

pulses with SCK in fixed high or fixed low state starts Nap

mode. Four or more pulses with SCK in fixed high or fixed

low state starts Sleep mode.

Reference Voltage vs VDD

VDD (V)

2.4890

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

2.8

3.0

3.2

3.4

1407 G12

2.6

3.6

Reference Voltage

vs Load Current

LOAD CURRENT (mA)

0.4

0.8

1.2

1.6

1407 G13

2.0

0.2

0.6

1.0

1.4

1.8

2.4890

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

VDD = 3V, TA = 25°C (LTC1407/LTC1407A)

TYPICAL PERFOR A CE CHARACTERISTICS

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