REV. A

AD7719

–20–

Table XI. Status Register Bit Designations

Bit

Bit

Location

Name

Description

SR7

RDY0

Ready Bit for Main ADC.

Set when data is written to main ADC data registers or on completion of calibration cycle. The RDY0 bit is

cleared automatically after the main ADC data register has been read or after a period of time before the

data register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to

indicate a conversion or calibration.

SR6

RDY1

Ready Bit for Aux ADC.

Set when data is written to aux ADC data registers or on completion of calibration cycle. The RDY1 bit is

cleared automatically after the aux ADC data register has been read or a period of time before the data register

is updated with a new conversion result. This bit is also cleared by a write to the mode bits to indicate a

conversion or calibration.

SR5

CAL

Calibration Status Bit.

Set to indicate completion of calibration. It is set at the same time that the RDY0 and/or RDY1 bits

are set high. Cleared by a write to the mode bits to start another ADC conversion or calibration.

SR4

NOXREF

No External Reference Bit. (Only active if main ADC is active and applies to REFIN1 only.)

Set to indicate that one or both of the REFIN1 pins is floating or the applied voltage is below a specified

threshold. When Set, conversion results are clamped to all 1s.

Cleared to indicate valid reference applied between REFIN1(+) and REFIN1(–).

SR3

ERR0

Main ADC Error Bit.

Set to indicate that the result written to the main ADC data registers has been clamped to all 0s or all 1s.

After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.

Error sources include Overrange, Underrange, and NOXREF.

Cleared by a write to the mode bits to initiate a conversion or calibration.

SR2

ERR1

Aux ADC Error Bit.

Set to indicate that the result written to the Aux ADC data registers has been clamped to all 0s or all 1s.

After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.

Error sources include Overrange, Underrange, and NOXREF.

Cleared by a write to the mode bits to initiate a conversion or calibration.

SR1

0

Reserved for Future Use.

SR0

LOCK

PLL Lock Status Bit.

Set if the PLL has locked onto the 32 kHz crystal oscillator clock. If the user is worried about exact sampling

frequencies, for example, the LOCK bit should be interrogated and the result discarded if the LOCK bit is 0.

Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On

Reset = 0x00)

The ADC Status register is an 8-bit read-only register. To access

the ADC Status register, the user must write to the Communica-

tions register selecting the next operation to be a read and loading

bits A3 to A0 with 0, 0, 0, 0. Table XI outlines the bit designations

for the Status register. SR0 through SR7 indicate the bit location,

with SR denoting that the bits are in the Status register. SR7

denotes the first bit of the data stream. The number in paren-

theses indicates the power-on/reset default status of that bit.

7

R

S6

R

S5

R

S4

R

S3

R

S2

R

S1

R

S0

R

S

)

0

(

0

Y

D

R)

0

(

1

Y

D

R)

0

(

L

A

C)

0

(

F

E

R

X

O

N)

0

(

0

R

R

E)

0

(

1

R

R

E)

0

()

0

(

K

C

O

L