MSK620 datasheet(3/6 Pages) ETC

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APPLICATION NOTES

Pin 6 is the video input pin. The video input signal is coupled

to this point through a 30Ω, 10µF 'RC' filter as shown in figure

two. The MSK 620 is designed to receive input voltages as

high as ±13.5V.

VIDEO INPUT

Pin 16 is the (-) clamp input pin. This pin is the inverting

input to the clamp comparator. A 10KΩ feedback resistor is

connected from this pin to the output pin of the amplifier (pin

14). When the clamp comparator is enabled, the voltage at pin

16 is compared to the voltage at pin 17, which is the non-

inverting input of the clamp comparator. A source or sink cur-

rent is generated at pin 10 to charge or discharge the clamp

cap and supply DC bias to the video amplifier. The DC voltage

at pin 17 is user adjustable through a 100KΩ potentiometer

voltage divider to Vref (see Figure 2). In DC coupled cathode

drive applications, brightness can be varied by varying the DC

voltage at pin 17.

CLAMP CONNECTIONS

Pin 11 is the clamp gate input pin and is driven by a TTL back

porch clamp signal. A voltage level of +1.3V or less is a "low

level" and a voltage level of +1.5V or greater is a "high level".

An active low level at this pin enables the clamp comparator

section so that DC restoration can be accomplished. This pin

should be held at a "high" logic level when a back porch clamp

signal is not used.

DC RESTORATION

Pins 15 is a no connect pin and should be tied to the nearest

available video ground plane.

NO CONNECT PINS

A typical single video channel connection diagram for the

MSK 620 is shown in Figure 1 above. The DC voltage at pin 6

is internally fixed at +2.6V and the video signal is AC coupled

to the input. An internal reference voltage generator supplies a

+5.0VDC level at pin 9 for use with the contrast, drive and

brightness control potentiometers. With pin 7 at 0V, minimum

gain is realized. With pin 7 at 4V, maximum gain is realized.

The clamp gate input at pin 11 accepts a TTL level clamp signal

for DC restoration during the back porch segment of the video

signal. Pin 17 is the brightness control input pin and accepts a

zero to four volt DC level. This level sets the black level of the

signal. If pin 17=+1VDC the signal black level will be +1VDC.

The 499Ω load resistor biases the class A output stage and

should be included during the power dissipation calculation stage.

499Ω is the minimum recommended value of load resistance

for the MSK 620.

Pin 10 is the clamp comparator output pin. A capacitance of

approximately 0.1µF is connected from this pin to ground. Dur-

ing the "back porch" portion of the clamp signal, the clamp

capacitor is either charged or discharged to match the voltage

set on the non-inverting input of the clamp comparator (pin

16). During the video portion of the input signal, the clamp

comparator is disabled and the clamp cap holds the proper DC

bias in the video amplifier.

CLAMP CAP

OUTPUT

Pin 14 is the video output pin. Since the output of the MSK

620 is a push pull design, there is no need for an external

pullup resistor. A 499Ω load resistor to analog ground will

optimize the output stage current level and bandwidth and is

highly recommended.

POWER SUPPLY CONNECTIONS

Pin 13 is the positive power supply pin. Convenient internal

power supply decoupling consists of a parallel combination of

three capacitors ranging from 0.01µF to 0.47µF. The user is

advised to connect at least a 4.7µF tantalum decoupling ca-

pacitor as close to the power supply pin as possible.

Vref OUTPUT

Pin 9 is the Vref output pin. This pin connects to the output

of an ultra stable 5.0VDC reference voltage generator internal

to the MSK 620. This reference is used as a voltage source for

the contrast, drive and clamp inputs.

Pin 8 is the drive control input. This pin accepts a DC voltage

to control overall gain. Pin 8 is internally decoupled to ground

with a 0.1uF capacitor. With 0V at pin 8, the gain is minimum

(-6dB). With 4V at pin 8, the gain is maximum (0dB). Drive

control is approximated by the following formula:

ATTENUATION (dB) = (1.5) x (DRIVE VOLTAGE) - (6dB)

See graph of Attenuation vs. Drive Control Voltage.

DRIVE CONTROL

CONTRAST CONTROL

To achieve contrast control, pin 1 is shorted to pin 2 and pin

3 is shorted to pin 4. The voltages at pins 1 and 4 are con-

trolled by the input voltage at pin seven. As the voltage at pin

7 increases, the voltages at pins 1 and 4 become offset. With

pin 7 at zero volts, pins 1 and 4 are at minimum offset and the

contrast is set to the minimum value of -38dB typical. With pin

7 at 4V, pins 1 and 4 are at maximum offset and contrast is

maximized to +26dB. Pin 7 is internally decoupled to ground

with a 0.1uF capacitor.

Rev. A 8/00

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