FDMF3035 datasheet(11/21 Pages) ONSEMI

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PWM

GH-PHASE

(internal)

BOOT-GND

VIH_PWM

VIL_PWM

90%

10%

tFALL_GH

tRISE_GL

tPD_PHGLL

tPD_PLGHL

tD_DEADOFF

tD_DEADON

tFALL_GL

tRISE_GH

90%

10%

90%

10%

90%

10%

tPD_PHGLL = PWM HI to GL LOW, VIH_PWM to 90% GL

tFALL_GL = 90% GL to 10% GL

tD_DEADON = LS Off to HS On Dead Time, 10% GL to

VBOOT-GND <= PVCC - VF_DBOOT - 1V

tRISE_GH = 10% GH to 90% GH, VBOOT-GND <= PVCC -

VF_DBOOT - 1V to VSW_PEAK

tPD_PLGHL = PWM LOW to GH LOW, VIL_PWM to 90%

GH, tPD_PLGLH - tD_DEADOFF - tFALL_GH

tFALL_GH = 90% GH to 10% GH

tD_DEADOFF = HS Off to LS On Dead Time, VSW <= 0V

to 10% GL

tPD_PLGLH = PWM LOW to GL HI, VIL_PWM to 10% GL

tRISE_GL = 10% GL to 90% GL

tPD_PLGLH

PVCC - VF_DBOOT - 1V

Figure 25.

PWM Timing Diagram

VIH_PWM

VTRI_HI

(9)

VTRI_LO

VIL_PWM

(12)

3-State

Window

3-State

Window

VIH_PWM

(11)

VTRI_HI

VTRI_LO

(10)

VIL_PWM

PWM

GH-PHASE

(7)

(8)

(7)

Figure 26.

PWM Threshold Definition

Notes:

The timing diagram in Figure 26 assumes very slow ramp on PWM.

Slow ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> tD_HOLD-OFF.

VTRI_HI = PWM trip level to enter 3-state on PWM falling edge.

VTRI_LO = PWM trip level to enter 3-state on PWM rising edge.

10. VIH_PWM = PWM trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.

11. VIL_PWM = PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.

FDMF3035 Datasheet(PDF) 11 Page - ON Semiconductor

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