OX16CF950 datasheet(12/60 Pages) ETC

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OXCF950 DATA SHEET V1.1

OXFORD SEMICONDUCTOR LTD.

5.3.3

Accessing Local Configuration Registers

The local configuration registers are a set of device specific registers, which can be accessed via standard IO mapping. As the

device is configured as a single function device, no base address is required to access the local configuration registers. Since IO

mapping is used, access to the local configuration registers is permitted only after the card has been configured. Once the

Configuration Options Register has been set in the Attribute area, the local configuration registers can be accessed following the

mapping shown in Table 5. This access is always permitted in Normal Mode. In Local Bus Mode access is only permitted if bit[0]

is set to ‘1’ in the MDR register in the UART, otherwise the local bus will be accessed rather than the local configuration

registers.

CF/PCMCIA offset from address 0 for local

configuration registers in IO space (hex)

EEPROM Status and Control register

Multi-Purpose I/O Configuration register

UART Divider/Interrupt Pulse Width Divider register

Mode Status register

Interrupt Status register

Soft UART/Local Bus reset register

Reserved

Table 5: Local Configuration Register's mapping in I/O space

Each of the local configuration registers are explained in the following sections

EEPROM Status and Control register ‘ESC’(Offset 0x08)

This register defines the control on the serial EEPROM. The individual bits are described in Table 6.

Read/Write

Bits

Description

EEPROM

PCMCIA

Reset

7:5

Reserved

000

EEPROM Data In.

For reads from the EEPROM this input bit is the output-data (DO) of the

external EEPROM connected to EE_DI pin

EEPROM Data Out.

For writes to the EEPROM, this output bit feeds the input-data of the

external EEPROM (DI). This bit is output on the devices EE_DO and

clocked into the EEPROM by EE_CK

R/W

EEPROM Clock.

For reads or writes to the external EEPROM toggle this bit to generate an

EEPROM clock (EE_CK pin)

R/W

EEPROM Chip Select.

When ‘1’ the EEPROM chip select pin EE_CS is activated (high). When ‘0’

EE_CS is de-activated (low)

R/W

EEPROM Valid

A ‘1’ indicates that a valid EEPROM program header is present

Table 6: EEPROM Status and Control Register

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