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AD7713 Datasheet(PDF) 6 Page - Analog Devices |
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AD7713 Datasheet(HTML) 6 Page - Analog Devices |
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6 / 29 page  REV. D AD7713 –5– TIMING CHARACTERISTICS1, 2 (DVDD = 5 V 5%; AVDD = 5 V or 10 V 5%; AGND = DGND = 0 V; fCLKIN = 2 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, S Versions) Unit Conditions/Comments fCLK IN 3, 4 400 kHz min Master Clock Frequency: Crystal Oscillator or 2 MHz max Externally Supplied for Specified Performance tCLK IN LO 0.4 tCLK IN ns min Master Clock Input Low Time; tCLK IN = 1/fCLK IN tCLK IN HI 0.4 tCLK IN ns min Master Clock Input High Time tr 5 50 ns max Digital Output Rise Time; Typically 20 ns tf 5 50 ns max Digital Output Fall Time; Typically 20 ns t1 1000 ns min SYNC Pulse Width Self-Clocking Mode t2 0 ns min DRDY to RFS Setup Time t3 0 ns min DRDY to RFS Hold Time t4 2 tCLK IN ns min A0 to RFS Setup Time t5 0 ns min A0 to RFS Hold Time t6 4 tCLK IN + 20 ns max RFS Low to SCLK Falling Edge t7 6 4 tCLK IN +20 ns max Data Access Time ( RFS Low to Data Valid) t8 6 tCLK IN/2 ns min SCLK Falling Edge to Data Valid Delay tCLK IN/2 + 30 ns max t9 tCLK IN/2 ns nom SCLK High Pulse Width t10 3 tCLK IN/2 ns nom SCLK Low Pulse Width t14 50 ns min A0 to TFS Setup Time t15 0 ns min A0 to TFS Hold Time t16 4 tCLK IN + 20 ns max TFS to SCLK Falling Edge Delay Time t17 4 tCLK IN ns min TFS to SCLK Falling Edge Hold Time t18 0 ns min Data Valid to SCLK Setup Time t19 10 ns min Data Valid to SCLK Hold Time External-Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 tCLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t24 6 4 tCLK IN ns max Data Access Time ( RFS Low to Data Valid) t25 6 10 ns min SCLK Falling Edge to Data Valid Delay 2 tCLK IN + 20 ns max t26 2 tCLK IN ns min SCLK High Pulse Width t27 2 tCLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t29 7 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS/TFS to SCLK Falling Edge Hold Time t31 7 5 tCLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 tCLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 tCLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 10 to 13. 3CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7713 is production tested with f CLK IN at 2 MHz. It is guaranteed by characterization to operate at 400 kHz. 5Specified using 10% and 90% points on waveform of interest. 6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. |
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