AD7713 datasheet(17/29 Pages) AD

17 / 29 page

REV. D

–16–

AD7713

look like the AIN1 analog input (see Figure 7). In this case, RINT

is 5 k

Ω typ and C

INT varies with gain. The input sample rate is

fCLK IN/256 and does not vary with gain. For gains of 1 to 8,

CINT is 20 pF; for a gain of 16, it is 10 pF; for a gain of 32, it is

5 pF; for a gain of 64, it is 2.5 pF; and for a gain of 128, it is

1.25 pF.

The digital filter of the AD7713 removes noise from the reference

input just as it does with the analog input, and the same limita-

tions apply regarding lack of noise rejection at integer multiples of

the sampling frequency. The output noise performance outlined

in Tables I and II assumes a clean reference. If the reference

noise in the bandwidth of interest is excessive, it can degrade the

performance of the AD7713. A recommended reference source

for the AD7713 is the AD680, a 2.5 V reference.

USING THE AD7713 SYSTEM

DESIGN CONSIDERATIONS

The AD7713 operates differently from successive approxima-

tion ADCs or integrating ADCs. Since it samples the signal

continuously, like a tracking ADC, there is no need for a start

convert command. The output register is updated at a rate

determined by the first notch of the filter, and the output can be

read at any time, either synchronously or asynchronously.

Clocking

The AD7713 requires a master clock input, which may be an

external TTL/CMOS compatible clock signal applied to the

MCLK IN pin with the MCLK OUT pin left unconnected.

Alternatively, a crystal of the correct frequency can be connected

between MCLK IN and MCLK OUT, in which case the clock

circuit will function as a crystal controlled oscillator. For lower

clock frequencies, a ceramic resonator may be used instead of the

crystal. For these lower frequency oscillators, external capacitors

may be required on either the ceramic resonator or on the crystal.

The input sampling frequency, the modulator sampling frequency,

the –3 dB frequency, output update rate, and calibration time

are all directly related to the master clock frequency, fCLK IN.

Reducing the master clock frequency by a factor of two will halve

the above frequencies and update rate and will double the cali-

bration time.

The current drawn from the DVDD power supply is also directly

related to fCLK IN. Reducing fCLK IN by a factor of two will halve

the DVDD current but will not affect the current drawn from the

AVDD power supply.

System Synchronization

If multiple AD7713s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the

SYNC input resets the filter

and places the AD7713 into a consistent, known state. A com-

mon signal to the AD7713’s

SYNC inputs will synchronize their

operation. This would normally be done after each AD7713 has

performed its own calibration or has had calibration coefficients

loaded to it.

The

SYNC input can also be used to reset the digital filter in

systems where the turn-on time of the digital power supply

(DVDD) is very long. In such cases, the AD7713 will start operat-

ing internally before the DVDD line has reached its minimum

operating level, 4.75 V. With a low DVDD voltage, the AD7713’s

internal digital filter logic does not operate correctly. Thus, the

AD7713 may have clocked itself into an incorrect operating

condition by the time that DVDD has reached its correct level.

The digital filter will be reset upon issue of a calibration,

command (whether it is self-calibration, system calibration or

background calibration) to the AD7713. This ensures correct

operation of the AD7713. In systems where the power-on default

conditions of the AD7713 are acceptable, and no calibration is

performed after power-on, issuing a

SYNC pulse to the AD7713

will reset the AD7713’s digital filter logic. An R, C on the

SYNC

line, with R, C time constant longer than the DVDD power-on

time, will perform the

SYNC function.

Accuracy

- ADCs, like VFCs and other integrating ADCs, do not contain

any source of nonmonotonicity, and inherently offer no missing

codes performance. The AD7713 achieves excellent linearity by

the use of high quality, on-chip silicon dioxide capacitors, which

have a very low capacitance/voltage coefficient. The device also

achieves low input drift through the use of chopper stabilized tech-

niques in its input stage. To ensure excellent performance over

time and temperature, the AD7713 uses digital calibration tech-

niques that minimize offset and gain error.

Autocalibration

Autocalibration on the AD7713 removes offset and gain

errors from the device. A calibration routine should be initi-

ated on the device whenever there is a change in the ambient

operating temperature or supply voltage. It should also be

initiated if there is a change in the selected gain, filter notch,

or bipolar/unipolar input range. However, if the AD7713 is in

its background calibration mode, the above changes are all

automatically taken care of (after the settling time of the filter

has been allowed for).

The AD7713 offers self-calibration, system calibration, and

background calibration facilities. For calibration to occur on

the selected channel, the on-chip microcontroller must record

the modulator output for two different input conditions. These

are zero-scale and full-scale points. With these readings, the

microcontroller can calculate the gain slope for the input to

output transfer function of the converter. Internally, the part

works with a resolution of 33 bits to determine its conversion

result of either 16 bits or 24 bits.

The AD7713 also provides the facility to write to the on-chip

calibration registers, and, in this manner, the span and offset for

the part can be adjusted by the user. The offset calibration register

contains a value that is subtracted from all conversion results, while

the full-scale calibration register contains a value that is multiplied

by all conversion results. The offset calibration coefficient is sub-

tracted from the result prior to the multiplication by the full-scale

coefficient. In the first three modes outlined here, the

DRDY line

indicates that calibration is complete by going low. If

DRDY is low

before (or goes low during) the calibration command, it may take

up to one modulator cycle before

DRDY goes high to indicate that

calibration is in progress. Therefore, the

DRDY line should be

ignored for up to one modulator cycle after the last bit of the cali-

bration command is written to the control register.

Self-Calibration

In the self-calibration mode with a unipolar input range, the

zero-scale point used in determining the calibration coefficients

is with both inputs shorted and the full-scale point is VREF. The

zero-scale coefficient is determined by converting an internal

shorted inputs node. The full-scale coefficient is determined

from the span between this shorted inputs conversion and a

conversion on an internal VREF node. The self-calibration mode

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