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AD7713 Datasheet(PDF) 21 Page - Analog Devices |
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AD7713 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 29 page ![]() REV. D –20– AD7713 signal must remain valid for the duration of the serial read opera- tion. With A0 high, data is accessed from either the output register or from the calibration registers. With A0 low, data is accessed from the control register. The function of the DRDY line is dependent on only the output update rate of the device and the reading of the output data register. DRDY goes low when a new data-word is available in the output data register. It is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. If data is not read from the output register, the DRDY line will remain low. The output register will continue to be updated at the output update rate, but DRDY will not indicate this. A read from the device in this circumstance will access the most recent word in the output register. If a new data-word becomes avail- able to the output register while data is being read from the output register, DRDY will not indicate this, and the new data- word will be lost to the user. DRDY is not affected by reading from the control register or the calibration register. Data can be accessed from the output data register only when DRDY is low. If RFS goes low while DRDY is high, no data transfer will take place. DRDY does not have any effect on read- ing data from the control register or from the calibration registers. Figures 12a and 12b show timing diagrams for reading from the AD7713 in the external clocking mode. Figure 12a shows a situation where all the data is read from the AD7713 in one read operation. Figure 12b shows a situation where the data is read from the AD7713 over a number of read operations. Both read operations show a read from the AD7713’s output data register. A read from the control register or calibration registers is similar, but in these cases, the DRDY line is not related to the read function. Depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affecting the read and its status should be ignored. A read operation from either the control or calibration registers must always read 24 bits of data from the respective register. Figure 12a shows a read operation from the AD7713 where RFS remains low for the duration of the data-word transmis- sion. With DRDY low, the RFS input is brought low. The input SCLK signal should be low between read and write operations. RFS going low places the MSB of the word to be read on the serial data line. All subsequent data bits are clocked out on a high-to-low transition of the serial clock and are valid prior to the following rising edge of this clock. The penultimate falling edge of SCLK clocks out the LSB and the final falling edge resets the DRDY line high. This rising edge of DRDY turns off the serial data output. Figure 12b shows a timing diagram for a read operation where RFS returns high during the transmission of the word and returns low again to access the rest of the data-word. Timing parameters and functions are very similar to that outlined for Figure 12a, but Figure 12b has a number of additional times to show timing relationships when RFS returns high in the middle of transferring a word. RFS should return high during a low time of SCLK. On the rising edge of RFS, the SDATA output is turned off. DRDY remains low and will remain low until all bits of the data-word are read from the AD7713, regardless of the number of times RFS changes state during the read operation. Depending on the time between the falling edge of SCLK and the rising edge of RFS, the next bit (BIT N + 1) may appear on the data bus before RFS goes high. When RFS returns low again, it activates the SDATA output. When the entire word is transmitted, the SDATA (O) SCLK (I) THREE-STATE RFS (I) A0 (I) t22 MSB LSB DRDY (O) t21 t20 t23 t26 t29 t28 t27 t25 t24 Figure 12a. External Clocking Mode, Output Data Read Operation THREE-STATE MSB BIT N BIT N+1 SDATA (O) SCLK (I) RFS (I) A0 (I) DRDY (O) t22 t20 t31 t26 t24 t25 t27 t30 t24 t25 Figure 12b. External Clocking Mode, Output Data Read ( RFS Returns High During Read Operation) |
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