AD7890

Rev. C | Page 10 of 28

CONTROL REGISTER

The control register for the AD7890 contains 5 bits of information.

Six serial clock pulses must be provided to the part in order to

write data to the control register (seven if the write is required

to put the part in standby mode). If TFS returns high before six

serial clock cycles, then no data transfer takes place to the

control register and the write cycle has to be restarted to write

the data to the control register.

If, however, the CONV bit of the register is set to a Logic 1, then

a conversion is initiated whenever a control register write takes

place regardless of how many serial clock cycles the TFS

remains low for. The default (power-on) condition of all bits in

the control register is 0.

MSB

LSB

A2

A1

A0

CONV

STBY

Table 3.

Bit Name

Description

A2

Address Input. This input is the most significant address input for multiplexer channel selection.

A1

Address Input. This is the 2nd most significant address input for multiplexer channel selection.

A0

Address Input. Least significant address input for multiplexer channel selection. When the address is written to the control

this pulse is active, it ensures the conversion process cannot be activated. This allows for the multiplexer settling time,

track/hold acquisition time before the track/hold goes into hold, and the conversion is initiated. In applications where there is

an antialiasing filter between the MUX OUT pin and the SHA IN pin , the filter settling time can be taken into account before the

input on the SHA IN pin is sampled. When the internal pulse times out, the track/hold goes into hold and conversion is initiated.

CONV

Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to the CONVST input. Continuous conversion

starts do not take place when there is a 1 in this location. The internal pulse and the conversion process are initiated after the

sixth serial clock cycle of the write operation if a 1 is written to this bit. With a 1 in this bit, the hardware conversion start (the

CONVST input) is disabled. Writing a 0 to this bit enables the hardware CONVST input.

STBY

Standby Mode Input. Writing a 1 to this bit places the device in its standby, or power-down, mode. Writing a 0 to this bit places

the device in its normal operating mode. The part does not enter its standby mode until the seventh falling edge of SCLK in a

write operation. Therefore, the part requires seven serial clock pulses in its serial write operation if it is required to put the part

into standby.