AD7890 datasheet(21/29 Pages) AD

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AD7890

Rev. C | Page 20 of 28

MICROPROCESSOR/MICROCONTROLLER INTERFACE

The AD7890’s flexible serial interface allows for easy

connection to the serial ports of DSP processors and

microcontrollers. Figure 14 through Figure 17 show the

AD7890 interfaced to a number of different microcontrollers

and DSP processors. In some of the interfaces shown, the

AD7890 is configured as the master in the system, providing

the serial clock and frame sync for the read operation while in

others it acts as a slave with these signals provided by the

microprocessor.

AD7890 TO 8051 INTERFACE

Figure 14 shows an interface between the AD7890 and the

8xC51 microcontroller. The AD7890 is configured for its

external clocking mode while the 8xC51 is configured for its

Mode 0 serial interface mode. The diagram shown in Figure 14

makes no provisions for monitoring when conversion is

complete on the AD7890 (assuming hardware conversion start

is used). To monitor the conversion time on the AD7890, a

scheme, such as the scheme outlined with CONVST in the

Simplifying the Interface section, can be used. This can be

implemented in two ways. One is to connect the CONVST line

to another parallel port bit, which is configured as an input.

This port bit can then be polled to determine when conversion is

complete. An alternative is to use an interrupt driven system where

the CONVST line is connected to the INT1 input of the 8xC51.

Since the 8xC51 contains only one serial data line, the DATA

OUT and DATA IN lines of the AD7890 must be connected

together. This means that the 8xC51 cannot communicate with

the output register and control register of the AD7890 at the

same time. The 8xC51 outputs the LSB first in a write operation

so care should be taken in arranging the data, which is to be

transmitted to the AD7890. Similarly, the AD7890 outputs the

MSB first during a read operation while the 8xC51 expects the

LSB first. Therefore, the data that is to be read into the serial

port needs to be rearranged before the correct data word from

the AD7890 is available in the microcontroller.

The serial clock rate from the 8xC51 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7890 can operate. As a result, the time to read data from

the part is actually longer than the conversion time of the part.

This means that the AD7890 cannot run at its maximum

throughput rate when used with the 8xC51.

VDD

SMODE

RFS

TFS

DATA OUT

DATA IN

SCLK

P1.0

P1.1

P3.0

P3.1

AD7890

8xC51

Figure 14. AD7890 to 8xC51 Interface

AD7890 TO 68HC11 INTERFACE

An interface circuit between the AD7890 and the 68HC11

microcontroller is shown in Figure 15. For the interface shown,

the AD7890 is configured for its external clocking mode while

the 68HC11’s SPI port is used and the 68HC11 is configured in

its single-chip mode. The 68HC11 is configured in the master

mode with its CPOL bit set to a Logic 0 and its CPHA bit set to

a Logic 1.

As with the previous interface, there are no provisions for

monitoring when conversion is complete on the AD7890. To

monitor the conversion time on the AD7890, a scheme, such as

the scheme outlined with CONVST in the Simplifying the

Interface section, can be used. This can be implemented in two

ways. One is to connect the CONVST line to another parallel

port bit, which is configured as an input. This port bit can then

be polled to determine when conversion is complete. An alternative

is to use an interrupt driven system in which case the CONVST

line should be connected to the IRQ input of the 68HC11.

DVDD

SMODE

RFS

TFS

DATA OUT

DATA IN

SCLK

PC0

PC1

SCK

MISO

MOSI

68HC11

AD7890

Figure 15. AD7890 to 68HC11 Interface

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