AD7890 datasheet(20/29 Pages) AD

20 / 29 page

AD7890

Rev. C | Page 19 of 28

SIMPLIFYING THE INTERFACE

To minimize the number of interconnect lines to the AD7890,

the user can connect the RFS and TFS lines of the AD7890

together and read and write from the part simultaneously. In

this case, new control register data should be provided on the

DATA IN line selecting the input channel and possibly

providing a conversion start command while the part provides

the result from the conversion just completed on the

DATA OUT line.

In the self-clocking mode, this means that the part provides all

the signals for the serial interface. It does require that the

microprocessor has the data to be written to the control register

available in its output register when the part brings the TFS line

low. In the external clocking mode, it means that the user only

has to supply a single frame synchronization signal to control

both the read and write operations.

Care must be taken with this scheme that the read operation is

completed before the next conversion starts, if the user wants to

obtain optimum performance from the part. In the case of the

software conversion start, the conversion command is written

to the control register on the sixth serial clock edge. However,

the read operation continues for another 10 serial clock cycles.

To avoid reading during the sampling instant or during

conversion, the user should ensure that the internal pulse width

is sufficiently long (by choosing CEXT) so that the read operation

is completed before the next conversion sequence begins.

Failure to do this results in significantly degraded performance

from the part, both in terms of signal-to-noise ratio and dc

parameters. In the case of a hardware conversion start, the user

should ensure that the delay between the sixth falling edge of

the serial clock in the write operation and the next rising edge

of CONVST is greater than the internal pulse width.

AD7890 Datasheet(PDF) 20 Page - Analog Devices