AD7890 datasheet(18/29 Pages) AD

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AD7890

Rev. C | Page 17 of 28

SERIAL INTERFACE

The AD7890’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7890 accesses data from the output

writes data to the control register via the DATA IN line.

Two different modes of operation are available, optimized for

different types of interface where the AD7890 can act either as

master in the system (it provides the serial clock and data

framing signal) or acts as slave (an external serial clock and

framing signal can be provided to the AD7890). The former is

self-clocking mode while the latter is external clocking mode.

SELF-CLOCKING MODE

The AD7890 is configured for its self-clocking mode by tying

the SMODE pin of the device to a logic low. In this mode, the

AD7890 provides the serial clock signal and the serial data

framing signal used for the transfer of data from the AD7890.

This self-clocking mode can be used with processors that allow

an external device to clock their serial port, including most

digital signal processors.

Read Operation

Figure 10 shows a timing diagram for reading from the AD7890

in the self-clocking mode. At the end of conversion, RFS goes

low and the serial clock (SCLK) and serial data (DATA OUT)

outputs become active. Sixteen bits of data are transmitted with

one leading zero, followed by the three address bits of the

control register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the

rising edge of SCLK and is valid on the falling edge of SCLK.

The RFS output remains low for the duration of the 16 clock

cycles. On the 16th rising edge of SCLK, the RFS output is driven

high and DATA OUT is disabled.

RFS (O)

SCLK (O)

DATA OUT (O)

THREE-STATE

LEADING

ZERO

DB0

DB10

DB11

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

Figure 10. Self-Clocking (Master) Mode Output Register Read

TFS (I)

SCLK (O)

DATA IN (I)

NOTES:

1. (I) SIGNIFIES AN INPUT.

2. (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

t10

t11

t12

CONV

STBY

DON’T

CARE

DON’T

CARE

DON’T

CARE

Figure 11. Self-Clocking (Master) Mode Control Register Write

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