IR3082

Page 11 of 11

12/17/04

IR3082 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3082 is shown in figure 7 and discussed in the following sections.

+

-

+

DISABLE

EAOUT

FB

ERROR

AMP

IFB

-

ISINK

ISOURCE

VDAC

BUFFER

AMP

+

"FAST"

VDAC

+

-

+

-

40uA

DISCHG

OC

IROSC

IROSC

IROSC

+

-

VBIAS

+

-

+

-

+

-

+

-

+

-

+-

+

-

+

-

1.270V

+

-

+

-

1.205V

+

-

+

-

+

-

ENABLE

VOSNS-

IIN

VID1

VCC

OCSET

LGND

ROSC

VID2

VID0

VDAC

RMPOUT

SS/DEL

PWRGD

VDRP

VBIAS

VID4

VID3

+

-

+

-

6uA

50%

DUTY

CYCLE

ON

1.24V

IDISCHG

1.0V

CURRENT

SOURCE

GENERATOR

RAMP GENERATOR

66uA

ON

SS/DEL

DISCHARGE

OC

COMPARATOR

7.0V

VCHG

3.9V

SOFTSTART

CLAMP

5.0V

VBIAS

REGULATOR

ICHG

VDRP

AMP

ROSC

BUFFER

AMP

0.225V

OFF

70mV

CURRENT

700ns

BLANKING

DIGITAL TO

ANALOG

CONVERTER

VCC

UVLO

COMPARATOR

9.75V

ENABLE

COMPARATOR

9.0V

IOCSET

VID INPUT

COMPARATORS

(1 OF 5

SHOWN)

V

I

D

=

O

F

F

DELAY

COMPARATOR

DISCHARGE

COMPARATOR

O

V

E

R

C

U

R

R

E

N

T

+

-

FAULT

LATCH

R

S

S

E

T

D

O

M

I

N

A

N

T

IHICCUP

1.3V

115mV

Figure 7 – IR3082 Block Diagram

VID Control

A 5-bit VID voltage compatible with AMD’s Opteron/Athlon64, as shown in Table 1, is available at the VDAC pin.

The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 1.2V

reference, monitor the VID pins and control the 6 bit Digital-to-Analog Converter (DAC) whose output is sent to the

VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is trimmed to compensate

for the input offsets of the Error Amp to provide 1% system set-point accuracy and is pre-positioned 50mV higher

than Vout listed in Table1 for load positioning. The actual VDAC voltage does not determine the system accuracy

and has a wider tolerance.

The IR3082 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The

sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator

frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC

pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC

buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter

output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage.