Electronic Components Datasheet Search
  English  ▼

X  

AD7292 Datasheet(PDF) 32 Page - Analog Devices

Part # AD7292
Description  10-Bit Monitor and Control System with ADC,DACs, Temperature Sensor, and GPIOs
PDF  41 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7292 Datasheet(HTML) 32 Page - Analog Devices

Back Button AD7292 Datasheet HTML 28Page - Analog Devices AD7292 Datasheet HTML 29Page - Analog Devices AD7292 Datasheet HTML 30Page - Analog Devices AD7292 Datasheet HTML 31Page - Analog Devices AD7292 Datasheet HTML 32Page - Analog Devices AD7292 Datasheet HTML 33Page - Analog Devices AD7292 Datasheet HTML 34Page - Analog Devices AD7292 Datasheet HTML 35Page - Analog Devices AD7292 Datasheet HTML 36Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 32 / 41 page
background image
Data Sheet
AD7292
ALERT FLAGS REGISTER BANK (ADDRESS 0x07)
If a conversion result activates an alert (as specified in the alert
limits register bank), the alert flags register bank can be read
to obtain more information about the alert. This register bank
contains the ADC alert flags and TSENSE alert flags subregisters.
Both subregisters store flags that are triggered when the mini-
mum or maximum conversion limits, as defined in the alert
limits register bank, are exceeded.
Table 32. Alert Flags Register Bank Subregisters
1
Bits in the alert flags subregisters can be reset by writing 1 to the selected bits.
ADC Alert Flags and TSENSE Alert Flags Subregisters
(Address 0x00 and Address 0x02)
The ADC alert flags subregister stores alerts for the analog volt-
age conversion channels, VIN0 to VIN7. The TSENSE alert flags
subregister stores alerts for the temperature sensor channel.
These subregisters contain two status bits per channel: one
corresponding to the high limit, and the other corresponding to
the low limit. A bit with a status of 1 shows the channel on which
the violation occurred and whether the violation occurred on the
high or low limit.
If additional alert events occur on any other channels after the
first alert is triggered but before the alert flags subregister is read,
the corresponding bits for the new alert events are also set. For
example, if Bit D14 in the ADC alert flags subregister is set to 1,
the low limit on Channel 7 has been exceeded, whereas if Bit D3
is set to 1, the high limit on Channel 1 has been exceeded.
To find out which channel or channels caused the alert flag, the
user must read the ADC alert flags subregister or the TSENSE alert
flags subregister. If the ADC alert flags subregister or the TSENSE
alert flags subregister is accessed with both the read and write bits
of the address pointer set to 1, the stored alert flags can be read
and reset in one operation. A blanket reset can be performed by
writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to
the TSENSE alert flags subregister, thus clearing all alert flags.
Table 33. ADC Alert Flags Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
Description
D15
VIN7 high limit flag
R/W
1 = VIN7 high limit exceeded
D14
VIN7 low limit flag
R/W
1 = VIN7 low limit exceeded
D13
VIN6 high limit flag
R/W
1 = VIN6 high limit exceeded
D12
VIN6 low limit flag
R/W
1 = VIN6 low limit exceeded
D11
VIN5 high limit flag
R/W
1 = VIN5 high limit exceeded
D10
VIN5 low limit flag
R/W
1 = VIN5 low limit exceeded
D9
VIN4 high limit flag
R/W
1 = VIN4 high limit exceeded
D8
VIN4 low limit flag
R/W
1 = VIN4 low limit exceeded
D7
VIN3 high limit flag
R/W
1 = VIN3 high limit exceeded
D6
VIN3 low limit flag
R/W
1 = VIN3 low limit exceeded
D5
VIN2 high limit flag
R/W
1 = VIN2 high limit exceeded
D4
VIN2 low limit flag
R/W
1 = VIN2 low limit exceeded
D3
VIN1 high limit flag
R/W
1 = VIN1 high limit exceeded
D2
VIN1 low limit flag
R/W
1 = VIN1 low limit exceeded
D1
VIN0 high limit flag
R/W
1 = VIN0 high limit exceeded
D0
VIN0 low limit flag
R/W
1 = VIN0 low limit exceeded
Table 34. TSENSE Alert Flags Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
Description
[D15:D2]
Reserved
R/W
Reserved
D1
TSENSE high limit flag
R/W
1 = TSENSE high limit exceeded
D0
TSENSE low limit flag
R/W
1 = TSENSE low limit exceeded
Subaddress (Hex)
Subregister Name1
0x00
ADC alert flags subregister
0x01
Reserved
0x02
TSENSE alert flags subregister
0x03 to 0xFF
Reserved
Rev. A | Page 31 of 40



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com