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Data Sheet

AD7292

ALERT FLAGS REGISTER BANK

The alert flags register bank contains two subregisters: the ADC

alert flags subregister and the TSENSE alert flags subregister. The

ADC alert flags subregister stores alerts for the analog voltage

conversion channels, VIN0 to VIN7. The TSENSE alert flags sub-

subregisters contain two status bits per channel: one correspond-

ing to the high limit, and the other corresponding to the low

limit (see Table 33 and Table 34). A bit with a status of 1 shows

the channel on which the violation occurred and whether the

violation occurred on the high or low limit.

If additional alert events occur on any other channels after the

first alert is triggered but before the alert flags subregister is read,

the corresponding bits for the new alert events are also set. For

example, if Bit D14 in the ADC alert flags subregister is set to 1,

the low limit on Channel 7 has been exceeded, whereas if Bit D3

is set to 1, the high limit on Channel 1 has been exceeded.

An alert associated with either the alert high limit or alert low

limit subregister is cleared automatically after the monitored

signal is back in range, that is, when the conversion result returns

between the configured high and low limits. The contents of the

alert flags subregister are updated after each conversion.

To find out which channel or channels caused the alert flag, the

user must read the ADC alert flags subregister or the TSENSE alert

flags subregister. If the ADC alert flags subregister or the TSENSE

alert flags subregister is accessed with both the read and write bits

of the address pointer set to 1, the stored alert flags can be read

and reset in one operation. A blanket reset can be performed by

writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to

the TSENSE alert flags subregister, thus clearing all alert flags.

MINIMUM AND MAXIMUM CONVERSION RESULTS

The read-only minimum/maximum register bank contains the

minimum and maximum conversion values for each of the eight

analog input channels and the temperature sensor channel.

Values are 10-bit, left justified.

The minimum and maximum subregisters are cleared when a

value is written to them—that is, they return to their power-up

values. This means that if a subregister is accessed with both the

read and write bits set, the stored minimum or maximum value

can be read and reset in one operation. On power-up, the mini-

mum value subregisters contain 0xFFC0, and the maximum value

subregisters contain 0x0000.

Rev. A | Page 39 of 40

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