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AD7292 Datasheet(PDF) 21 Page - Analog Devices |
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AD7292 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 41 page  AD7292 Data Sheet REGISTER STRUCTURE The AD7292 contains internal registers that store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 39). Each register has an address; the address pointer register points to the address when communicating with the register. Some registers and sub- registers contain reserved bits. The AD7292 allows either a 0 or a 1 to be written to these reserved bits. ADDRESS POINTER REGISTER SERIAL BUS INTERFACE DIN SCLK VENDOR ID REGISTER ADC DATA ADC SEQUENCE REGISTER GPIO REGISTER CONFIGURATION REGISTER BANK OFFSET REGISTER BANK TSENSE CONVERSION RESULT REGISTER ADC CONVERSION RESULT REGISTERS × 8 CONVERSION COMMAND DAC BUFFER ENABLE REGISTER DAC CHANNEL REGISTERS × 4 ALERT LIMITS REGISTER BANK ALERT FLAGS REGISTER BANK MINIMUM AND MAXIMUM REGISTER BANK DOUT CS Figure 39. AD7292 Register Structure Table 14 lists each register and specifies whether the register has read access or read and write access. Table 14. AD7292 Registers Address Register Name Access1 Data Format 0x00 Vendor ID register R Figure 36 0x01 ADC data register R Figure 36 0x03 ADC sequence register R/W Figure 36 0x05 Configuration register bank R/W Figure 38 0x06 Alert limits register bank R/W Figure 38 0x07 Alert flags register bank R/W Figure 38 0x08 Minimum and maximum register bank R/W Figure 38 0x09 Offset register bank R/W Figure 37 0x0A DAC buffer enable register R/W Figure 36 0x0B GPIO register R/W Figure 36 0x0E Conversion command2 N/A N/A 0x10 ADC conversion result register, Channel 0 R Figure 36 0x11 ADC conversion result register, Channel 1 R Figure 36 0x12 ADC conversion result register, Channel 2 R Figure 36 0x13 ADC conversion result register, Channel 3 R Figure 36 0x14 ADC conversion result register, Channel 4 R Figure 36 0x15 ADC conversion result register, Channel 5 R Figure 36 0x16 ADC conversion result register, Channel 6 R Figure 36 0x17 ADC conversion result register, Channel 7 R Figure 36 0x20 TSENSE conversion result register R Figure 36 0x30 DAC Channel 0 register R/W Figure 36 0x31 DAC Channel 1 register R/W Figure 36 0x32 DAC Channel 2 register R/W Figure 36 0x33 DAC Channel 3 register R/W Figure 36 1 R is read only; R/W is read/write. 2 See the ADC Conversion Command section for more information. Rev. A | Page 20 of 40 |
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