AD9278 datasheet(29/45 Pages) AD

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AD9278

Data Sheet

Rev. A | Page 28 of 44

0.1µF

CMOS DRIVER

OPTIONAL

100Ω

0.1µF

CLK

*50Ω RESISTOR IS OPTIONAL.

AD951x FAMILY

3.3V

OUT

VFAC3

CLK–

CLK+

AD9278

50Ω*

Figure 54. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9278 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9278. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See Table 19 for more details on

using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated as follows:

SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 55).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9278.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources, such as the Valpey Fisher VFAC3 series.

If the clock is generated from another type of source (by gating,

dividing, or other methods), it should be retimed by the original

clock during the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about how

jitter performance relates to ADCs (visit www.analog.com).

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

0.25ps

Figure 55. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 56 and Figure 57, the power dissipated by

the AD9278 is proportional to its sample rate. The digital power

dissipation does not vary significantly because it is determined

primarily by the DRVDD supply and the bias current of the

LVDS output drivers.

100

150

200

250

300

SAMPLING FREQUENCY (MSPS)

IAVDD1, MODE I, fSAMPLE = 40MSPS

IAVDD1,MODE II, fSAMPLE = 25MSPS

IAVDD1, MODE III, fSAMPLE =50MSPS

IAVDD1, MODE IV, fSAMPLE = 65MSPS

IDRVDD

Figure 56. Supply Current vs. fSAMPLE for fIN = 5 MHz

100

105

110

SAMPLING FREQUENCY (MSPS)

MODE IV,

fSAMPLE = 65MSPS

MODE III,

fSAMPLE = 50MSPS

MODE II,

fSAMPLE = 25MSPS

MODE I,

fSAMPLE = 40MSPS

Figure 57. Power per Channel vs. fSAMPLE for fIN = 5 MHz

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