AD9278 datasheet(30/45 Pages) AD

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Data Sheet

AD9278

Rev. A | Page 29 of 44

The AD9278 features scalable LNA bias currents (see Table 19,

Figure 58 shows the typical reduction of AVDD2 current with

each bias setting. It is also recommended that the LNA offset be

adjusted using Register 0x10 (see Table 19) when the LNA bias

setting is low.

HIGH

MID-HIGH

MID-LOW

LOW

102

104

106

108

110

112

114

116

118

TOTAL AVDD2 CURRENT (mA)

Figure 58. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 40 MSPS

By asserting the PDWN pin high, the AD9278 is placed into

power-down mode. In this state, the device typically dissipates

5 mW. During power-down, the LVDS output drivers are placed

into a high impedance state. The AD9278 returns to normal

operating mode when the PDWN pin is pulled low. This pin

is both 1.8 V and 3.3 V tolerant.

By asserting the STBY pin high, the AD9278 is placed into a

standby mode. In this state, the device typically dissipates

420 mW. During standby, the entire part is powered down

except the internal references. The LVDS output drivers are

placed into a high impedance state. This mode is well suited for

applications that require power savings because it allows the

device to be powered down when not in use and then quickly

powered up. The time to power the device back up is also greatly

reduced. The AD9278 returns to normal operating mode when

the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V

tolerant.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on VREF are discharged

when entering power-down mode and must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in the power-down mode: shorter

cycles result in proportionally shorter wake-up times. To restore

the device to full operation, approximately 0.5 ms is required

when using the recommended 1 µF and 0.1 µF decoupling

capacitors on the VREF pin and the 0.01 µF decoupling

capacitors on the GAIN± pins. Most of this time is dependent

on the gain decoupling: higher value decoupling capacitors on

the GAIN± pins result in longer wake-up times.

A number of other power-down options are available when

using the SPI port interface. The user can individually power

down each channel or put the entire device into standby mode.

This allows the user to keep the internal PLL powered up when

fast wake-up times are required. The wake-up time is slightly

dependent on gain. To achieve a 1 µs wake-up time when the

device is in standby mode, 0.8 V must be applied to the GAIN±

pins. See Table 19 for more details on using these features.

Power and Ground Recommendations

When connecting power to the AD9278, it is recommended that

two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one 1.8 V supply is

available, it should be routed to the AVDD1 pin first and then

tapped off and isolated with a ferrite bead or a filter choke

preceded by decoupling capacitors for the DRVDD pin. The

user should employ several decoupling capacitors on all

supplies to cover both high and low frequencies. Locate these

capacitors close to the point of entry at the PCB level and close

to the part, with minimal trace lengths.

A single PCB ground plane should be sufficient when using the

AD9278. With proper decoupling and smart partitioning of the

analog, digital, and clock sections of the PCB, optimum perfor-

mance can be easily achieved.

Digital Outputs and Timing

The AD9278 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This can be changed to

a low power, reduced signal option similar to the IEEE 1596.3

standard via the SPI, using Register 0x14, Bit 6. This LVDS

standard can further reduce the overall power dissipation of the

device by approximately 36 mW.

The LVDS driver current is derived on chip and sets the output

current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing at the receiver.

The AD9278 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point network topologies are recommended with

a 100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length be no longer than 24 inches and that the

differential output traces be kept close together and at equal

lengths. An example of the FCO (CH2), DCO (CH1), and data

(CH3) stream with proper trace length and position is shown in

Figure 59.

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