AD9674KBCZ datasheet(7/48 Pages) AD

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AD9674

Data Sheet

Rev. A | Page 6 of 47

Parameter2

Test Conditions/Comments

Min

Typ

Max

Unit

Close In SNR

−3 dBFS input, fRF = 2.5 MHz,

fLO = 40 MHz, 1 kHz offset,

16LO5 mode, one channel enabled

156

dBc/√Hz

−3 dBFS input, fRF = 2.5 MHz,

fLO = 40 MHz, 1 kHz offset,

16LO5 mode, eight channels enabled

161

dBc/√Hz

Two-Tone Intermodulation Distortion

(IMD3)

fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,

fLO = 80 MHz, ARF1 = −1 dBFS,

ARF2 = −21 dBFS, IMD3 relative to ARF2

−58

dBc

LO Harmonic Rejection

−20

dBc

Quadrature Phase Error

I to Q, all phases, 1 σ

0.15

Degrees

I/Q Amplitude Imbalance

I to Q, all phases, 1 σ

0.015

Channel to Channel Matching

Phase I to I, Q to Q, 1 σ

0.5

Degrees

Amplitude I to I, Q to Q, 1 σ

0.25

POWER SUPPLY

Mode I/Mode II/Mode III/Mode IV1, 3

AVDD1

1.7

1.8

1.9

AVDD2

2.85

3.0

3.6

DVDD

1.3

1.4

1.9

DRVDD

1.7

1.8

1.9

IAVDD1

TGC mode, LO band mode

144/188/224/2943

CW Doppler mode

IAVDD2

TGC mode, no signal, low band mode

230

TGC mode, no signal, high band mode

239

CW Doppler mode, eight channels

enabled

140

IDVDD

RF decimator enabled in Mode III1 and

Mode IV,1 digital HPF enabled

47/75/57/913

RF decimator enabled in Mode III1 and

Mode IV,1 digital HPF disabled

30/48/42/653

IDRVDD

ANSI-644 mode

125/170/128/1693

Low power (IEEE 1596.3 similar) mode

109/155/114/1543

Total Power Dissipation (Including

Output Drivers)

TGC mode, no signal, RF decimator

enabled in Mode III and Mode IV,

digital HPF disabled

1190/1385/

1365/16003

1325/1535/

1515/17653

TGC mode, no signal, RF decimator

enabled in Mode III1 and Mode IV, 1

digital HPF enabled

1215/1425/

1385/16403

1350/1575/

1535/18003

CW Doppler mode, eight channels

enabled

500

Power-Down Dissipation

Standby Power Dissipation

630

ADC

Resolution

Bits

SNR

fIN = 5 MHz

ADC REFERENCE

Output Voltage Error

VREF = 1 V

±50

Load Regulation at 1.0 mA

VREF = 1 V

Input Resistance

7.5

kΩ

The ADC speed modes depending on the encoding clock rate.

For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, UnderstandingHigh SpeedADCTestingandEvaluation.

The slashes mean that the four different power and current values are listed for the four different modes (Mode I, Mode II, Mode III, Mode IV).

The overrange condition is specified as 6 dB more than the full-scale input range.

The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be

4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly.

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