Data Sheet

AD9674

Rev. A | Page 7 of 47

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), unless

otherwise noted.

Table 2.

Temperature

Min

Typ

Max

Unit

INPUTS (CLK+, CLK−, TX_TRIG+, TX_TRIG−)

Logic Compliance

Full

CMOS/LVDS/LVPECL

Full

0.2

3.6

V p-p

Input Voltage Range

Full

GND − 0.2

AVDD1 + 0.2

V

Input Common-Mode Voltage

Full

0.9

V

Input Resistance (Differential)

25°C

15

kΩ

Input Capacitance

25°C

4

pF

INPUTS (MLO±, RESET±)

Logic Compliance

Full

LVDS/LVPECL

Full

0.250

2 × AVDD2

V p-p

Input Voltage Range

Full

GND − 0.2

AVDD2 + 0.2

V

Input Common-Mode Voltage

Full

AVDD2/2

V

Input Resistance (Single-Ended)

25°C

20

kΩ

Input Capacitance

25°C

1.5

pF

LOGIC INPUTS (PDWN, STBY, SCLK, SDIO, ADDRx)

Logic 1 Voltage

Full

1.2

DRVDD + 0.3

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

30 (26 for SDIO)

kΩ

Input Capacitance

25°C

2 (5 for SDIO)

pF

LOGIC INPUT (CSB)

Logic 1 Voltage

Full

1.2

DRVDD + 0.3

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

26

kΩ

Input Capacitance

25°C

2

pF

Full

1.79

V

Full

0.05

V

DIGITAL OUTPUTS (DOUTx+, DOUTx−), ANSI-644

Logic Compliance

Full

LVDS

Full

247

454

mV

Full

1.125

1.375

V

Output Coding (Default)

Full

Offset binary

DIGITAL OUTPUTS (DOUTx+, DOUTx−), LOW POWER,

REDUCED SIGNAL OPTION

Logic Compliance

Full

LVDS

Full

150

250

mV

Full

1.10

1.30

V

Output Coding (Default)

Full

Offset binary

LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)

Full

Full

0.05

V

1

For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, UnderstandingHigh SpeedADCTestingandEvaluation.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.