AD9675 datasheet(29/61 Pages) AD

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AD9675

Data Sheet

Rev. A | Page 28 of 60

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. Calculate the degradation in SNR at a given input

frequency (fA) due only to aperture jitter (tJ) as follows:

SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)

(7)

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter (see Figure 43).

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9675. Separate

power supplies for clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

Low jitter, crystal controlled oscillators make the best clock

sources, such as the Valpey Fisher VFAC3 series. If the clock is

generated from another type of source (by gating, dividing, or

other methods), it is retimed by the original clock during the

last step.

For more information on how jitter performance relates to

ADCs, refer to the AN-501 Application Note and the AN-756

Application Note.

Figure 43. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

The power dissipated by the AD9675 is proportional to its

sample rate. The digital power dissipation does not vary

significantly because it is determined primarily by the DRVDD

supply and the bias current of the LVDS output drivers. The

AD9675 features scalable LNA bias currents (see Table 31,

Address 0x012). The default LNA bias current settings are

midhigh.

By asserting the PDWN pin high, the AD9675 is placed into

power-down mode. In this state, the device typically dissipates

5 mW. During power-down, the LVDS output drivers are placed

into a high impedance state. The AD9675 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

only 1.8 V tolerant. To drive the PDWN pin from a 3.3 V logic

level, insert a 1 kΩ resistor in series with this pin to limit the

current.

By asserting the STBY pin high, the AD9675 is placed in standby

mode. In this state, the device typically dissipates 725 mW.

During standby, the entire device is powered down except the

internal references. The LVDS output drivers are placed into a

high impedance state. This mode is well suited for applications

that require power savings because it allows the device to be

powered down when not in use and then quickly powers up.

The time to power up the device is also greatly reduced. The

AD9675 returns to normal operating mode when the STBY pin

is pulled low. This pin is only 1.8 V tolerant. To drive the STBY

pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with

this pin to limit the current.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on VREF are discharged

when entering power-down mode and must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in power-down mode: shorter cycles

result in proportionally shorter wake-up times. To restore the

device to full operation, approximately 375 μs is required when

using the recommended 1 μF and 0.1 μF decoupling capacitors

on the VREF pin and the 0.01 μF decoupling capacitors on the

GAIN± pins. Most of this time is dependent on gain decoupling;

higher value decoupling capacitors on the GAIN± pins result in

longer wake-up times.

A number of other power-down options are available when using

the SPI port interface. The user can individually power down

each channel or place the entire device into standby mode. When

fast wake-up times are required, standby mode allows the user

to keep the internal PLL powered up. The wake-up time is slightly

dependent on gain. To achieve a 2 μs wake-up time when the

device is in standby mode, apply 0.8 V to the GAIN± pins.

Power and Ground Connection Recommendations

When connecting power to the AD9675, use two separate 1.8 V

supplies: one for analog (AVDD1) and one for digital (DRVDD).

If only one 1.8 V supply is available, route it to the AVDD1 pin

first and then tap it off and isolate it with a ferrite bead or a filter

choke preceded by decoupling capacitors for the DRVDD pin.

The DVDD pin can be tied to the 1.8 V DRVDD supply. When

this is done, route the DVDD supply first, tap it off, and isolate

it with a ferrite bead or filter choke preceded by decoupling

capacitors for the DRVDD pin. It is not recommended to use

the same supply for AVDD1, DVDD, and DRVDD. For

compatibility with the AD9671 or for lower power operation,

the DVDD pin can be tied to 1.4 V.

For both high and low frequencies, use several decoupling

capacitors on all supplies. Place these capacitors near the point

of entry at the PCB level and near the device, with minimal

trace lengths.

When using the AD9675, a single PCB ground plane is sufficient.

With proper decoupling and smart partitioning of the analog,

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.5ps

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

8BITS

RMS CLOCK JITTER REQUIREMENT

0.25ps

AD9675 Datasheet(PDF) 29 Page - Analog Devices

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