AP3776 datasheet(11/17 Pages) DIODES

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AP3776

Document number: DS36707 Rev. 4 - 2

11 of 17

www.diodes.com

February 2015

AP3776

A Product Line of

Diodes Incorporated

Function Description (Cont.)

VCSREF

IOMAX

fSW

24kHz

60kHz

5 kHz

56.7 kHz

VCS_H =0.45V

=2/3*0.45V

=4/9*0.45V

20kHz

1.8%*IO

17.8%*IO

42%*IO

100%*IO

VCS_M

VCS_L

Figure 4. Multiple Segment Peak Current at CV Mode

The LL Mode Operating (Typical Application with APR343)

At no load and light load, the AP3776 works in Low Light mode (LL mode) and the output voltage is detected by APR343. In order to achieve

ultra low standby power in LL mode, the static current (ICC_NL) of the AP3776 is reduced from 280μA to 100μA.

• The conditions of exiting LL mode---VCPC>65mV or tOFF<tDELAY+30μs

• The conditions of entering LL mode---VCPC<33mV and tOFF≥tDELAY+30μs

In LL mode, when the APR343 detects the output voltage is lower than its trigger voltage, the APR343 VDET pin emits a periodical pulse

current. This pulse current will generate a pulse voltage on feedback winding through the transformer coupling. When the AP3776 detects this

VPULSE (>100mV is valid), primary switch immediately turns on to provide one energy pulse to supply output terminal and primary VCC. To

achieve low standby power, the lower switching frequency is necessary. But if the off time is too long, the VCC voltage will reduce to very low

level. To avoid VCC being lower than VOPR(Min), a minimum switching frequency is specified by the APR343 (tDIS). If VOUT does not fall below

trigger voltage during tDIS, APR343 VDET pin will emit the periodical pulse current and let the primary switch turn on.

Leading Edge Blanking

When the power switch is turned on, a turn-on spike will occur on the sense-resistor. To avoid false-termination of the switching pulse, a 500ns

leading-edge blanking (from power MOSFET on) is built in. During this blanking period, the current sense comparator is disabled and the gate

driver can’t be switched off.

Adjustable Line Compensation

Since there is a constant delay time from the CS pin voltage reaching the given VCS reference to the power MOSFET turning off, the real

primary peak current value always has a gap with the ideal value. The gap value changes with different input line voltage, which is caused by

different current rising slope, results in different system constant current value.

In order to eliminate the constant current deviation due to line voltage, the adjustable line compensation is introduced to AP3776 design. By

sensing the negative voltage of FB pin which is linear to the line voltage, a current (ILINE) proportional to line voltage flows out from the CS pin to

the resistor RLINE, and create an adjustable compensation voltage to clear up the primary current gap, so that the excellent line regulation of

output current will be achieved.

indc

aux

LINE

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