AD841

Data Sheet

Rev. C | Page 10 of 16

THEORY OF OPERATION

OFFSET NULLING

The input offset voltage of the AD841 is very low for a high

speed op amp, but if additional nulling is required, the circuit

shown in Figure 28 can be used.

Figure 28. Offset Nulling (PDIP Pinout)

INPUT CONSIDERATIONS

where the input to the AD841 is subjected to transient or

continuous overload voltages exceeding the ±6 V maximum

differential limit. This resistor provides protection for the input

transistors by limiting the maximum current that can be forced

into the input.

For high performance circuits it is recommended that a resistor

errors by matching the impedance at each input. The output

voltage error caused by the offset current is more than an order

of magnitude less than the error present if the bias current error

is not removed.

AD841 SETTLING TIME

Figure 29 and Figure 31 show the settling performance of the

AD841 in the test circuit shown in Figure 30.

Settling time is defined as the interval of time from the

application of an ideal step function input until the closed-loop

amplifier output has entered and remains within a specified

error band.

This definition encompasses the major components, which

comprise settling time. They include

•

Propagation delay through the amplifier

•

Slewing time to approach the final output value

•

The time of recovery from the overload associated

with slewing

•

Linear settling to within the specified error band

Expressed in these terms, the measurement of settling time

is obviously a challenge and needs to be done accurately to

assure the user that the amplifier is worth consideration for

the application.

Figure 29. AD841 0.01% Settling Time

Figure 30. Settling Time Test Circuit

Measurement of the 0.01% settling in 110 ns was accomplished

by amplifying the error signal from a false summing junction

with a very high speed proprietary hybrid error amplifier

specially designed to enable testing of small settling errors.

The device under test was driving a 500 Ω load. The input to

the error amp is clamped to avoid possible problems associated

with the overdrive recovery of the oscilloscope input amplifier.

The error amp gains the error from the false summing junction

by 10, and it contains a gain vernier to fine trim the gain.

11

12

3

4

5

10

–

+

AD841

6

2.2µF

0.1µF

INPUT

OUTPUT

100Ω

100Ω

100

90

10

0%

10mV

5V

20ns

OUTPUT ERROR:

0.02%/DIV

OUTPUT:

5V/DIV

DDD5109

FLAT-TOP

PULSE

GENERATOR

11

6

4

5

10

–

+

AD841

+15V

–15V

2.2µF

0.1µF

2.2µF

0.1µF

499Ω

50Ω

499Ω

1kΩ

1kΩ

1kΩ

1kΩ

ERROR

AMP

(×10)

TEK

7A13

TEK

7A18

HP6263

FET PROBE

TEK P6201