AD8367S datasheet(14/19 Pages) AD

14 / 19 page

Figure 6. Noise Figure and Input Third-Order Intercept vs. Gain Voltage (RSOURCE

= 200 Ω)

To maximize the AC swing at the output of the AD8367S, the output level is centered midway between ground and

the supply. This is achieved when the DECL pin is bypassed to ground via a shunt capacitor. The loop acts to

suppress deviations from the reference at outputs below its corner frequency while not affecting signals above it, as

shown in Figure 7. The maximum corner frequency with no external capacitor is 500 kHz. The corner frequency can

be lowered by adding an external capacitor, CHP:

Equation 4:

fHP(kHz) = 10 / (CHP(nF) + 0.02

A 100 Ω resistor in series with the CHP capacitor is recommended to de-Q the resonant tank that is formed by the

bond-wire inductance and CHP. Failure to insert this capacitor can potentially cause oscillations at higher frequencies

at high gain settings.

Figure 7. The dc output level is centered to midsupply by a control loop

whose corner frequency is determined by CHP.

The AD8367S contains a square-law detector that senses the output signal and compares it to a calibrated setpoint of

354 mVrms, which corresponds to a 1 Vp-p sine wave. This set point is internally set and cannot be modified to

change the AGC setpoint and the resulting VOUT level without using additional external components.

Any difference between the output and setpoint generates a current that is integrated by an external capacitor, CAGC,

connected from the DETO pin to ground, to provide an AGC control voltage. There is also an internal 5 pF capacitor

on the DETO pin. The resulting voltage is used as an AGC bias. For this application, the MODE pin is pulled low and

the DETO pin is tied to the GAIN pin. The output signal level is then regulated to 354 mVrms. The AGC bias

represents a calibrated rms measure of the received signal strength (RSSI). Since in AGC mode the output signal is

forced to the 354 mVrms setpoint (-9.02 dBVrms), Equation 2 can be recast to express the strength of the received

signal, VIN-RMS, in terms of the AGC bias VDETO.

Equation 5: VIN-RMS(dBVrms) = -54.02 + 50 x VDETO

where -54.02 dBVrms = -45 dB – 9.02 dBVrms.

For small changes in input signal level, VDETO responds with a characteristic single-

pole time constant, ᴛAGC, which is

proportional to CAGC.

AD8367S Datasheet(PDF) 14 Page - Analog Devices