AD8367S datasheet(18/19 Pages) AD

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Figure 12: AGC Response to a 32 dB step in input level (f = 50 MHz)

It is important to understand that RAGC does not act as if in shunt with CAGC. Rather, the error-correction process is that

of a true integrator, to guarantee an output that is exactly equal in rms amplitude to the specified setpoint. For large

changes in input level, the integrating action of this loop is most apparent. The slew rate of VAGC is determined by the

peak output current from the detector and the capacitor. Thus, for a representative value of CAGC = 3 nF, this rate is

about 20 Vrms or 10 dB/us, while the small-signal bandwidth is 1 kHz.

Most AGC loops incorporating a true error-integrating technique have a common weakness. When driven from an

increasingly larger signal, the AGC bias increases to reduce the gain. However, eventually the gain falls to its

minimum value, for which further increase in this bias has no effect on the gain. That is, the voltage on the loop

capacitor is forced progressively higher because the detector output is a current, and the AGC bias is its integral.

Consequently, there is always a precipitous increase in this bias voltage when the input to the AD8367S exceeds that

value that overdrives the detector, and because the minimum gain is -2.5 dB, that happens for all inputs 2.5 dB

greater than the setpoint of about 350 mVrms. If possible, the user should ensure that this limitation is preserved,

preferably with a guard-band of 5 dB to 10 dB below overload.

In some cases, if driven into AGC overload, the AD8367S requires unusually long times to recover; that is, the voltage

at DETO remains at an abnormally high value and the gain is at its lowest value. To avoid this situation, it is

recommended that a clamp be placed on the DETO pin, as shown in Figure 13.

Figure 13. External Clamp to prevent AGC Overload. The resistive divider network,

RA and RB, should be designed such that the base of Q1 is driven to 0.5 V.

AD8367S Datasheet(PDF) 18 Page - Analog Devices