Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Bus LVDS Output DC Specifications

V

OD

Output Differential

Voltage (DO+) -

(DO-)

Figure 10,R

Ω

450

500

550

mV

∆V

OD

Output Differential

Voltage Unbalance

215

mV

V

OS

Offset Voltage

1.05

1.2

1.25

V

∆V

OS

Offset Voltage

Unbalance

2.7

15

mV

Q

POV

Pre-Emphasis Output

Voltage Ratio

|V

Pre-Emphasis Level = 1

1.10

1.24

1.35

Pre-Emphasis Level = 2

1.35

1.47

1.55

Pre-Emphasis Level = 3

1.55

1.70

1.80

Pre-Emphasis Level = 4

1.80

1.91

1.95

Pre-Emphasis Level = 5

1.95

2.08

2.20

Pre-Emphasis Level = 6

2.10

2.21

2.35

Pre-Emphasis Level = 7

2.15

2.30

2.50

I

OS

Output Short Circuit

Current

DO = 0V, Din = H, PWDN and EN = 2.4V

-10

-25

-75

mA

I

OZ

TRI-STATE Output

Current

PWDN or EN = 0.8V, DO = 0V (Note 4)

-10

+10

µA

PWDN or EN = 0.8V, DO = VDD (Note 4)

-55

+55

µA

Power Supply Current (DVDD, PVDD and AVDD Pins)

I

DD

Total Supply Current

(includes load

current)

C

R

Ω

f = 66 MHz, PRBS-15

Pattern

160

225

mA

f = 66 MHz, Worst

Case Pattern

(Checker-Board

Pattern)

180

mA

I

DDP

Total Supply Current

with Pre-Emphasis

(includes load

current)

C

R

Ω

f = 66 MHz, PRBS-15

Pattern

240

mA

f = 66 MHz, Worst

Case Pattern

(Checker-Board

Pattern)

280

325

mA

I

DDX

Supply Current

Powerdown

PWDN = 0.8V, EN = 0.8V

1.0

3.0

mA

Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

TCP

Transmit Clock

Period

15.2

T

66.7

ns

t

TCIH

Transmit Clock High

Time

0.4T

0.5T

0.6T

ns

t

TCIL

Transmit Clock Low

Time

0.4T

0.5T

0.6T

ns

t

CLKT

TCLK Input

Transition Time

36

ns

t

JIT

TCLK Input Jitter

(Note 5)

80

ps (RMS)

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