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SL28541BZCT Datasheet(PDF) 16 Page - Silicon Laboratories

Part # SL28541BZCT
Description  Clock Generator for Intel짰Mobile Chipset
PDF  31 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28541BZCT Datasheet(HTML) 16 Page - Silicon Laboratories

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SL28541
...................... DOC #: SP-AP-0063 (Rev. AA) Page 16 of 31
Dial-A-Frequency® (CPU and SRC Clocks)
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
Associated Register Bits
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Table 7. PLL3/SE Configuration Table
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
Pin 24 (17) MHz Pin 25 (18) MHz Spread (%)
Comment
0
0000
PLL3 Disabled
0
0001
100
100
0.5
SRC1 from SRC_Main
0
0010
100
100
0.5
LCD_100 from PLL3
0
0011
100
100
1
LCD_100 from PLL3
0
0100
100
100
1.5
LCD_100 from PLL3
0
0101
100
100
2
LCD_100 from PLL3
0
0110
N/A
N/A
N/A
N/A
0
0111
N/A
N/A
N/A
N/A
0
1000
N/A
N/A
N/A
N/A
0
1001
N/A
N/A
N/A
N/A
0
1010
N/A
N/A
N/A
N/A
0
1011
N/A
N/A
N/A
N/A
0
1100
N/A
N/A
none
N/A
0
1101
N/A
N/A
N/A
N/A
0
1110
N/A
N/A
N/A
N/A
0
1111
N/A
N/A
N/A
N/A
1
0000
N/A
N/A
N/A
1
0001
27M_NSS
27M_SS
0.5
27M_SS from PLL3
1
0010
27M_NSS
27M_SS
0.5
27M_SS from PLL3
1
0011
27M_NSS
27M_SS
1
27M_SS from PLL3
1
0100
27M_NSS
27M_SS
1.5
27M_SS from PLL3
1
0101
27M_NSS
27M_SS
2
27M_SS from PLL3
1
0110
N/A
N/A
N/A
1
0111
N/A
N/A
N/A
1
1000
N/A
N/A
N/A
1
1001
N/A
N/A
N/A
1
1010
N/A
N/A
N/A
1
1011
N/A
N/A
N/A
1
1100
N/A
N/A
N/A
1
1101
N/A
N/A
N/A



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