Document Number: 002-14824 Rev. *J

Page 39 of 50

CYW20730

Reference

Characteristics

Symbol

Min

Max

Unit

1

Output setup time, from MOSI



data valid to sample edge of SCLK

Tds_mo

–

50

–

ns

2

Output hold time, from sample



edge of SCLK to MOSI data update

Tdh_mo

–

120

–

ns

3

Input setup time, from MISO



data valid to sample edge of SCLK

Tds_mi

–

TBD

–

ns

4

Input hold time, from sample



edge of SCLK to MISO data update

Tdh_mi

–

TBD

–

ns

Time from CS assert to first SCLK edge

Tsu_cs

½ SCLK period – 1

–

–

ns

6c

Time from first SCLK edge to CS

deassert

Thd_cs

½ SCLK period

–

–

ns

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by

configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.