Document Number: 002-14824 Rev. *J

Page 13 of 50

CYW20730

1.11.3 Internal Reset

Figure 4. Internal Reset Timing

1.11.4 External Reset

The CYW20730 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external

active low reset signal, RESET_N, can be used to put the CYW20730 in the reset state. The RESET_N pin has an internal pull-up

resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the

VDDO supply voltage level has been stabilized.

Figure 5. External Reset Timing

VDDO

VDDO POR

VDDC

VDDO POR threshold

VDDO POR delay

~ 2 ms

VDDC POR

VDDC POR threshold

VDDC POR delay

~ 2 ms

Baseband Reset

Crystal 

warm‐up 

delay: 

~ 5 ms

Crystal Enable

Start reading EEPROM and 

firmware boot

RESET_N

Pulse width

>50 µs

Crystal Enable

Baseband Reset

Start reading EEPROM and 

firmware boot

Crystal 

warm‐up 

delay: 

~ 5 ms