CYW43340 datasheet(81/96 Pages) CYPRESS

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Document Number: 002-14943 Rev. *L

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PRELIMINARY

CYW43340

16.6 LNLDO

Table 40. LNLDO Specifications

Specification

Notes

Min

Typ

Max

Units

Input supply voltage, Vin

Min = 1.2Vo + 0.1V = 1.3V.

Dropout voltage requirement must be met under

maximum load.

1.3

1.35

1.5

Output current

–

0.1

–

104

Output voltage, Vo

Programmable in 25 mV steps.

Default = 1.2V

1.1

1.2

1.275

Dropout voltage

At maximum load

–

100

Output voltage DC

accuracya

a.Load from 0.1 to 104 mA.

includes line/load regulation, load from 0.1 to

150 mA

–4

–

Quiescent current

No load

–

µA

Line regulation

Vin from (Vo + 0.1V) to 1.5V, max load

–

mV/V

Load regulation

Load from 1 mA to 104 mA

–

µV/mA

Leakage current

Power-down

–

µA

Output noise

@30 kHz, 60 mA load, Co = 1 µF

@100 kHz, 60 mA load, Co = 1 µF

–

nV/root-Hz

PSRR

@ 1kHz, input > 1.3V, Co= 1 µF,

Vo = 1.2V

–

Start-up time of PMU

VIO up and steady. Time from the REG_ON rising

edge to the LNLDO reaching 1.2V. Includes 256

µs vddc_ok_o delay.

–

1106

µs

LDO turn-on time

Chip already powered up.

–

180

µs

In-rush current during turn-on

From its output capacitor in a fully-discharged

state

––

150

External output capacitor,

Cob

b.Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details.

Total ESR (trace/capacitor): 30–200 mΩ

0.67c

c.The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

–

µF

External input capacitor

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from the CBUCK

output.

Total ESR (trace/capacitor): 30–200 mΩ

–1

–

µF

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