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ADNS2051 Datasheet(PDF) 18 Page - Agilent(Hewlett-Packard) |
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ADNS2051 Datasheet(HTML) 18 Page - Agilent(Hewlett-Packard) |
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18 / 40 page ![]() 18 Read Operation A read operation, which means that data is going from the ADNS-2051 to the micro- controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is written by the micro-controller, and has a “0” as its MSB to indicate data direction. The second byte con- tains the data and is driven by the ADNS-2051. The transfer is syn- chronized by SCLK. SDIO is changed on falling edges of SCLK and read on every rising edge of SCLK. The micro-controller must go to a high Z state after the last address data bit. The ADNS-2051 will go to the high Z state after the last data bit (see detail “B” in Figure 28). One other thing to note during a read operation is that SCLK will need to be delayed after the last address data bit to ensure that the ADNS-2051 has at least 100 µs to prepare the requested data. This is shown in the timing diagrams below. Figure 27. Read operation. Figure 28. Microcontroller to ADNS-2051 SDIO handoff. Figure 29. ADNS-2051 to microcontroller SDIO handoff. Note: The 120 ns high state of SCLK is the minimum data hold time of the ADNS-2051. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-2051 will hold the state of D0 on the SDIO line until the falling edge of SCLK. In both write and read operations, SCLK is driven by the micro-controller. Serial port communications is not allowed while PD (power down) is high. See “Error Detection and Recovery” regarding re-synchronizing via PD. D7 D6 A0 A1 DETAIL "A" MICROCONTROLLER TO ADNS-2051 SDIO HANDOFF SDIO SCLK 60 ns, MIN. tHOLD 100 µs, MIN. 120 ns, MIN. 0 ns, MIN. 120 ns, MAX. 0 ns, MIN. 120 ns, MAX. Hi-Z D0 10 ns, MAX. 120 ns, MIN. R/W BIT OF NEXT ADDRESS SCLK SDIO DETAIL "B" ADNS-2051 TO MICROCONTROLLER SDIO HANDOFF DRIVEN BY MICRO RELEASED BY 2051 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 D4 D3 D2 D1 SCLK CYCLE # SCLK SDIO SDIO DRIVEN BY MICRO-CONTROLLER SDIO DRIVEN BY ADNS-2051 DETAIL "A" DETAIL "B" |
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