ADNS2051 datasheet(21/40 Pages) HP

21 / 40 page

Error Detection and Recovery

1. The ADNS-2051 and the

micro-controller might get

out of synchronization due to

ESD events, power supply

droops or micro-controller

firmware flaws. In such a

case, the micro-controller

should raise PD for 100

µs.

The ADNS-2051 will reset the

serial port but will not reset

the registers and be prepared

for the beginning of a new

transmission.

2. The ADNS-2051 has a transac-

tion timer for the serial port.

If the sixteenth SCLK rising

edge is spaced more than

approximately 0.9 seconds

from the first SCLK edge of the

current transaction, the serial

port will reset.

3. Invalid addresses:

– Writing to an invalid

address will have no effect.

Reading from an invalid

address will return all zeros.

4. Collision detection on SDIO

– The only time that the

ADNS-2051 drives the SDIO

line is during a READ

operation. To avoid data

collisions, the micro-

controller should relinquish

SDIO before the falling edge

of SCLK after the last

address bit. The

ADNS-2051 begins to drive

SDIO after the next rising

edge of SCLK. The

ADNS-2051 relinquishes

SDIO within 120 ns of the

falling SCLK edge after the

last data bit. The micro-

controller can begin driving

SDIO any time after that. In

order to maintain low power

consumption in normal

operation or when the PD

pin is pulled high, the

micro-controller should not

leave SDIO floating until the

next transmission (although

that will not cause any

communication difficulties).

5. In case of synchronization

failure, both the ADNS-2051

and the micro-controller may

drive SDIO. The ADNS-2051

can withstand 30 mA of short

circuit current and will with-

stand infinite duration short

circuit conditions.

6. Termination of a transmission

by the micro-controller may

sometimes be required (for

example, due to a USB sus-

pend interrupt during a read

operation). To accomplish this

the micro-controller should

raise PD. The ADNS-2051 will

not write to any register and

will reset the serial port (but

nothing else) and be prepared

for the beginning of future

transmissions after PD goes

low.

7. The micro-controller can verify

success of write operations by

issuing a read command to the

same address and comparing

written data to read data.

8. The micro-controller can verify

the synchronization of the

serial port by periodically

reading the product ID

Notes on Power up and the Serial

Port

The sequence in which VDD, PD,

SCLK, and SDIO are set during

powerup can affect the operation

of the serial port. The diagram

below shows what can happen

shortly after powerup when the

microprocessor tries to read data

from the serial port.

This diagram shows the VDD ris-

ing to valid levels, at some point

the microcontroller starts its pro-

gram, sets the SCLK and SDIO

lines to be outputs, and sets them

high. It then waits to ensure that

the ADNS-2051 has powered up

and is ready to communicate. The

microprocessor then tries to read

from location 0x00, Product_ID,

Figure 35. Power up serial port watchdog timer sequence.

DATA = 0x02

SCLK

SDIO

ADDRESS = 0x00

VDD

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