2

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

The ICS952703 is a two chip clock solution for desktop designs using SiS741 style chipsets. When used with a zero delay

buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals

for such a system.

The ICS952703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the

first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the

use of a serially programmable I

output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each

individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting

under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

General Description

Block Diagram

PLL2

Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

ZCLK (1:0)

X1

X2

XTAL

CPU_STOP#

PCI_STOP#

SCLK

SEL24_48MHZ

SEL12_48MHz

PD#

FS (3:0)

MODE

SDATA

Control

Logic

PCICLK (5:0)

AGPCLK (1:0)

12_48MHZ

24_48MHZ

REF (2:0)

CPUCLKODC0

SRCCLKT

SRCCLKC

CPUCLKODT (1:0)

IOAPIC (1:0)

PCICLKF (1:0)