3

Integrated

Circuit

Systems, Inc.

ICS952703

Preliminary Product Preview

0813B—05/17/05

Pin Description

PIN # PIN NAME

PIN

TYPE

DESCRIPTION

1

VDDREF

PWR

Ref, XTAL power supply, nominal 3.3V

2

**FS0/REF0

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

3

**FS1/REF1

I/O

Frequency select latch input pin / 14.318 MHz reference clock.

4

**Mode/REF2

I/O

Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output.

5

GNDREF

PWR

Ground pin for the REF outputs.

6

X1

IN

Crystal input, Nominally 14.318MHz.

7

X2

OUT

Crystal output, Nominally 14.318MHz

8

GNDZ

PWR

Ground pin for the ZCLK outputs

9

ZCLK0

OUT

3.3V Hyperzip clock output.

10

ZCLK1

OUT

3.3V Hyperzip clock output.

11

VDDZ

PWR

Power supply for ZCLK clocks, nominal 3.3V

12

SCLK

IN

Clock pin of I2C circuitry 5V tolerant

13

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

14

*FS2/PCICLK_F0

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

15

*FS3/PCICLK_F1

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

16

PCICLK0

OUT

PCI clock output.

17

PCICLK1

OUT

PCI clock output.

18

GNDPCI

PWR

Ground pin for the PCI outputs

19

VDDPCI

PWR

Power supply for PCI clocks, nominal 3.3V

20

PCICLK2

OUT

PCI clock output.

21

*(PCI_STOP#)PCICLK3

I/O

Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This

input is activated by the MODE selection pin / PCI clock output.

22

*(CPU_STOP#)PCICLK4

I/O

Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This

input is activated by the MODE selection pin / PCI clock output.

23

*(PD#)PCICLK5

I/O

Asynchronous active low input pin used to power down the device into a low power state /

PCI clock output.

24

GNDPCI

PWR

Ground pin for the PCI outputs

25

GND48

PWR

Ground pin for the 48MHz outputs

26

24_48MHz/SEL24_48#MHz**~

I/O

24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.

27

12_48MHz/SEL12_48#MHz*

I/O

12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz.

28

AVDD48

PWR

Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V

29

VDDAGP

PWR

Power supply for AGP clocks, nominal 3.3V

30

AGPCLK1

OUT

AGP clock output

31

AGPCLK0

OUT

AGP clock output

32

GNDAGP

PWR

Ground pin for the AGP outputs

33

SDATA

I/O

Data pin for I2C circuitry 5V tolerant

34

IREF

OUT

This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed

precision resistor tied to ground in order to establish the appropriate current.

35

AGND

PWR

Analog Ground pin for Core PLL

36

AVDD

PWR

3.3V Analog Power pin for Core PLL

37

CPUCLKODC0

OUT

"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need

an external 1.5V pull-up.

38

CPUCLKODT0

OUT

True clock of differential pair CPU outputs. These open drain outputs need an external

1.5V pull-up.

39

GNDCPU

PWR

Ground pin for the CPU outputs

40

CPUCLKODT1

OUT

True clock of differential pair CPU outputs. These open drain outputs need an external

1.5V pull-up.

41

GND

PWR

Ground pin.

42

SRCCLKC

OUT

Complement clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

43

SRCCLKT

OUT

True clock of differential pair for S-ATA support.

+/- 300ppm accuracy required.

44

VDDSRC

PWR

Supply for SRC clocks, 3.3V nominal

45

GNDAPIC

PWR

Ground pin for the IOAPIC outputs.

46

IOAPIC0

OUT

IOAPIC clock outputs, norminal 2.5V.

47

IOAPIC1

OUT

IOAPIC clock outputs, norminal 2.5V.

48

VDDLAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.

* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength