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ICS952703 Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS952703 Datasheet(HTML) 8 Page - Integrated Circuit Systems |
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8 / 17 page ![]() 8 Integrated Circuit Systems, Inc. ICS952703 Preliminary Product Preview 0813B—05/17/05 I 2C Table: Byte Count Register Bit 7 BC7 RW 0 Bit 6 BC6 RW 0 Bit 5 BC5 RW 0 Bit 4 BC4 RW 0 Bit 3 BC3 RW 1 Bit 2 BC2 RW 1 Bit 1 BC1 RW 1 Bit 0 BC0 RW 1 I 2C Table: WD Time Control & Async Frequency Selection Register Bit 7 Reserved Reserved RW 0 Bit 6 ASYNC1 RW 0 Bit 5 ASYNC0 RW 0 Bit 4 Reserved Reserved RW 0 Bit 3 WDTCtrl Watch Dog Time base Control RW 0 Bit 2 WD2 WD Timer Bit 2 RW 1 Bit 1 WD1 WD Timer Bit 1 RW 1 Bit 0 WD0 WD Timer Bit 0 RW 1 Fix PLL Async Freq Programming bits See Table 2: Asynchronous Frequency Selection Table - Type Type Name PWD Byte 9 Pin # Name - - - - PWD Byte 8 Pin # - Byte Count Programming b(7:0) - - - - - - - - - - - Control Function Control Function 0 1 01 Reserved Reserved These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. 290ms Base - 1160ms Base Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. I 2C Table: VCO Control Select Bit & WD Timer Control Register Bit 7 M/NEN M/N Programming Enable RW 0 Bit 6 WDEN Watchdog Enable RW 0 Bit 5 WDStatus WD Alarm Status R 0 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 0 Bit 2 WD SF2 RW 0 Bit 1 WD SF1 RW 0 Bit 0 WD SF0 RW 0 PWD Type Byte 10 Pin # Control Function Name - - - - - - - Watch Dog Safe Freq Programming bits - 01 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). Disable Disable Normal Alarm Enable Enable Table 2: Asynchronous Frequency Selection Table B9 bit6 B9 bit5 SRC ZCLK AGP PCI 0 0 Main PLL Main PLL Main PLL Main PLL 0 1 100 133.33 66.66 33.33 1 0 100 150.00 75 37.5 1 1 100 133.33 80 40 |
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