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LP6283 Datasheet(PDF) 9 Page - Lowpower Semiconductor inc |
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LP6283 Datasheet(HTML) 9 Page - Lowpower Semiconductor inc |
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9 / 10 page ![]() LP6283–00 Version 0.0 Jul.-2016 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 9 of 10 Preliminary Datasheet LP6283 VDLY = 3V, GVOFF = 0 40 DRN Input Current DRN = 8V, VDLY = 3V, VGHM > DRN, GVOFF = 0 0 1 μA VGH Switch On-Resistance VDLY = GVOFF = 3V 5 10 Ω DRN Switch On-Resistance VDLY = 3V, GVOFF = 0, VGHM= 28V, VTHR = 1.4V 20 50 Ω VGHM Stop Level 10 x VTHR V Voltage Detector (XAO) Detecting Voltage Adjustment VDET Falling edge 1.25 V Detecting Voltage Accuracy −1 1 % VCOMP OPAmp Supply Voltage Range VIN-OP 4.5 18 V Supply Current IQ-OP 3 mA Input Offset Voltage VOS VCOM = AVDD/2 20 mV Input Bias Current IBias 1 100 nA Output Voltage Swing High VOH ILoad = 10mA VSUP −100 mV Output Voltage Swing Low VOL ILoad = −10mA 100 mV Short-Circuit Current To AVDD/2 Source or Sink for 1ms 300 mA -3dB Bandwidth F3dB RL = 10k Ω, CL= 10pF 20 MHz Gain Bandwidth Product GBW RL = 10k Ω, CL = 10pF 8 MHz Slew Rate 45 V/ μs HVLDO Quiescent Current IQ 40 μA LDO Feedback Reference Voltage VREF_FB 1.25 V Feedback Voltage Tolerance −0.5 0.5 % Output Current Limit VREF_I= 15V, VREF_O= 14V, ROUT= 50 Ω 60 mA Dropout Voltage VDrop ILoad = 60mA 0.5 V Power Supply Rejection Rate PSRR VREF_I = VREF_O + 1V, IOUT= 10mA 60 dB Switching-Frequency Selection FSEL Input Levels FSEL = High 1.5 V FSEL = Low 0.6 FSEL Pull High Current 1 μA Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. The device is not guaranteed to function outside its operating conditions. Note 3. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four layers test board. The case position of θJC is on the exposed pad of the package. |
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