ATAR092 datasheet(7/100 Pages) ATMEL

7 / 100 page

ATAR092/ATAR892

4535C–4BMCU–02/04

Figure 7.

ALU Zero-address Operations

I/O Bus

The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-

cation between the core and the on-chip peripherals takes place via the I/O bus and the

associated I/O control. With the MARC4 IN and OUT instructions the I/O bus allows a

direct read or write access to one of the 16 primary I/O addresses. More about the I/O

access to the on-chip peripherals is described in the section “Peripheral Modules”. The

I/O bus is internal and is not accessible by the customer on the final microcontroller

device, but it is used as the interface for the MARC4 emulation (see also the section

“Emulation”).

Instruction Set

The MARC4 instruction set is optimized for the high level programming language

qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to

generate a fast and compact program code. The CPU has an instruction pipeline allow-

ing the controller to prefetch an instruction from ROM at the same time as the present

instruction is being executed. The MARC4 is a zero-address machine, the instructions

contain only the operation to be performed and no source or destination address fields.

The operations are implicitly performed on the data placed on the stack. There are one

and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4

machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions

are only one byte long and are executed in a single machine cycle. For more information

refer to the “MARC4 Programmer’s Guide”.

Interrupt Structure

The MARC4 can handle interrupts with eight different priority levels. They can be gener-

ated from the internal and external interrupt sources or by a software interrupt from the

CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the

service routine in the ROM (see Figure 3 on page 9). The programmer can postpone the

processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt

occurrence will still be registered, but the interrupt routine only started after the I flag is

set. All interrupts can be masked, and the priority individually software configured by

programming the appropriate control register of the interrupting module (see section

“Peripheral Modules”).

Interrupt Processing

For processing the eight interrupt levels, the MARC4 includes an interrupt controller with

two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller

samples all interrupt requests during every non-I/O instruction cycle and latches these in

the interrupt pending register. If no higher priority interrupt is present in the interrupt

active register, it signals the CPU to interrupt the current program execution. If the inter-

rupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this

cycle a short call (SCALL) instruction to the service routine is executed and the current

PC is saved on the return stack.

TOS-1

CCR

RAM

TOS-2

TOS-3

TOS

ALU

TOS-4

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