ATAR092 datasheet(63/100 Pages) ATMEL

63 / 100 page

ATAR092/ATAR892

4535C–4BMCU–02/04

Figure 64. MCL Bus Protocol 1

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition

Stop data transfer (3)

A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

Data valid (4)

The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge

All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

Figure 65. MCL Bus Protocol 2

SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,

transmit buffer empty or receive buffer full), the end of SSI data telegram or on the fall-

ing edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed

by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually used to synchro-

nize the software control of the SSI and inform the controller of the present SSI status.

The Port 4 interrupts can be used together with the SSI or, if the SSI itself is not

required, as additional external interrupt sources. In either case this interrupt is capable

of waking the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and

the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropri-

ate control bits in P4CR register.

(2)

(1)

(4)

(3)

(1)

Start

condition

Data

valid

Data

change

Data

valid

Stop

condition

Start

1n8

1st Bit

8th Bit

ACK

Stop

ATAR092 Datasheet(PDF) 63 Page - ATMEL Corporation

ATAR092 Datasheet(HTML) 63 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL