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MP2110 Datasheet(PDF) 13 Page - Monolithic Power Systems

Part # MP2110
Description  3A Synchronous Step-Down Converter with Programmable Input Current Limit
PDF  15 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2110 Datasheet(HTML) 13 Page - Monolithic Power Systems

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MP2110 – 3A SYNCHRONOUS BUCK CONVERTER WITH INPUT CURRENT LIMIT
MP2110 Rev. 1.11
www.MonolithicPower.com
13
9/26/2014
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
Using ceramic capacitors, the impedance at the
switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification,
the output voltage ripple can be estimated by:
OUT
OUT
OUT
2
S1
IN
VV
ΔV1
8f
L
C3
V
⎛⎞
=× −
⎜⎟
×× ×
⎝⎠
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
OUT
OUT
OUT
ESR
IN
S1
VV
ΔV1
R
fL
V
⎛⎞
=× −
×
⎜⎟
×
⎝⎠
The characteristics of the output capacitor also
affect the stability of the regulation system.
PC Board Layout
PCB layout is very important to achieve stable
operation. For best results, follow these
guidelines and use Figure 2 as reference:
1) Use large ground plane directly connect to
PGND pin. Add vias near the PGND pin if
bottom layer is ground plane.
2) Place the ceramic input capacitor close to
SYSIN/REGIN and PGND pins. Keep the
connection
of
input
capacitor
and
SYSIN/REGIN pin as short and wide as
possible.
3) Route SW away from sensitive analog
areas such as FB, OUT pins. It’s not
recommended to route SW trace under
chip’s bottom side.
4) Place the feedback resistors close to chip
to ensure the trace which connects to FB
pin as short as possible.
C2
C3
VOUT
VOUT
Top Layer
Bottom Layer
GND
SYSIN
GND
GND
REGIN
C2A
R6
R1
R2
C4
R4
RNTC
C1
C1A
C3
C3A
L1
Figure 2: PCB Layout
Design Example
Below is a design example following the
application guidelines for the specifications:
Table 4—Design Example
VIN
5V
VOUT
3.6V
IOUT
3A
The detailed application schematic is shown in
Figure 3. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheet.



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