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PAC5232 Datasheet(PDF) 40 Page - Active-Semi, Inc |
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PAC5232 Datasheet(HTML) 40 Page - Active-Semi, Inc |
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40 / 66 page ![]() Power Application Controller -40- Rev 1.1 6-Jan-2018 signals according to Table 12-2, with configurable delays as shown in Table 12-3 Power Driver Propagation Delay. Refer to the PAC5232 User Guide and PAC ® application notes and user guide for additional information on power drivers control programming. Table 12-2 Microcontroller Port and PWM to Power Driver Mapping PART NUMBER DRL0 DRL1 DRL2 DRH3 DRH4 DRH5 PAC5232 PWMA0 PWMA1 PWMA2 PWMA3/ PWMA4/ PWMB0 PWMA5/ PWMC0 PWMA6/ PWMD0 Table 12-3 Power Driver Propagation Delay DRLx DRHx 135ns 155ns 12.7 Gate Driver Fault Protection The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable Analog Front End (CAFE), designated as protection event 1 (PR) signal. The DRL0/DRL1/DRL2 drivers are designated as low-side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The PR signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR mask bit settings. 12.8 Electrical Characteristics Table 12-4 Gate Driver Electrical Characteristics (VP = 12V, and TA = -40C to 105C unless otherwise specified.) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT Low-Side Gate Drivers (DRLx pins) VOH;DRL High-level output voltage IDRLx = -50mA VP-0.3 V VOL;DRL Low-level output voltage IDRLx = 50mA 0.3 V IOHPK;DRL Output high source current 10 s pulse 2 A IOLPK;DRL Output low sink current 10 s pulse 2 A High-Side Gate Drivers (DRHx, DRBx and DRSx pins) VDRS Level-shift driver source voltage range -10 VM + 10 V VDRB Bootstrap pin voltage range Relative to VDRS 10 20 V Relative to VSS 175 V VUVLO;DRB Bootstrap UVLO threshold VDRBx rising 8.5 V Hysteresis 1 V IBS;DRB Bootstrap supply current Current from DRBx to DRSx 28 A |
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