DS26503LN datasheet(2/123 Pages) DALLAS

2 / 123 page

DS26503 T1/E1/J1 BITS Element

2 of 123

TABLE OF CONTENTS

FEATURES .......................................................................................................................7

1.1

GENERAL ........................................................................................................................7

1.2

LINE INTERFACE...............................................................................................................7

1.3

JITTER ATTENUATOR ........................................................................................................7

1.4

FRAMER/FORMATTER .......................................................................................................8

1.5

TEST AND DIAGNOSTICS ...................................................................................................8

1.6

CONTROL PORT ...............................................................................................................8

SPECIFICATIONS COMPLIANCE ...................................................................................9

BLOCK DIAGRAMS .......................................................................................................12

PIN FUNCTION DESCRIPTION .....................................................................................15

4.1

TRANSMIT PLL...............................................................................................................15

4.2

TRANSMIT SIDE..............................................................................................................15

4.3

RECEIVE SIDE................................................................................................................16

4.4

CONTROLLER INTERFACE................................................................................................17

4.5

JTAG ...........................................................................................................................21

4.6

LINE INTERFACE.............................................................................................................21

4.7

POWER .........................................................................................................................22

PINOUT...........................................................................................................................23

HARDWARE CONTROLLER INTERFACE....................................................................26

6.1

TRANSMIT CLOCK SOURCE .............................................................................................26

6.2

INTERNAL TERMINATION..................................................................................................26

6.3

LINE BUILD-OUT.............................................................................................................27

6.4

RECEIVER OPERATING MODES........................................................................................27

6.5

TRANSMITTER OPERATING MODES ..................................................................................28

6.6

MCLK PRE-SCALER ......................................................................................................28

6.7

OTHER HARDWARE CONTROLLER MODE FEATURES .........................................................29

PROCESSOR INTERFACE ............................................................................................30

7.1

PARALLEL PORT FUNCTIONAL DESCRIPTION.....................................................................30

7.2

SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION .................................................30

7.2.1

Clock Phase and Polarity ................................................................................................... 30

7.2.2

Bit Order............................................................................................................................. 30

7.2.3

Control Byte ....................................................................................................................... 30

7.2.4

Burst Mode......................................................................................................................... 30

7.2.5

Register Writes................................................................................................................... 31

7.2.6

Register Reads ..................................................................................................................31

7.3

REGISTER MAP ..............................................................................................................32

7.3.1

Power-Up Sequence .......................................................................................................... 34

7.3.2

Test Reset Register............................................................................................................ 34

7.3.3

Mode Configuration Register.............................................................................................. 35

7.4

INTERRUPT HANDLING ....................................................................................................38

7.5

STATUS REGISTERS .......................................................................................................38

7.6

INFORMATION REGISTERS ...............................................................................................39

7.7

INTERRUPT INFORMATION REGISTERS..............................................................................39

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