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DS26503LN Datasheet(PDF) 39 Page - Dallas Semiconductor |
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DS26503LN Datasheet(HTML) 39 Page - Dallas Semiconductor |
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39 / 123 page  DS26503 T1/E1/J1 BITS Element 39 of 123 7.6 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. INFO3 register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3 information bits are not latched, and it is not necessary to precede a read of these bits with a write. 7.7 Interrupt Information Registers The Interrupt Information Registers provide an indication of which Status Registers (SR1 through SR3) are generating an interrupt. When an interrupt occurs, the host can read IIR to quickly identify which of the three status registers are causing the interrupt. Register Name: IIR Register Description: Interrupt Information Register Register Address: 13h Bit # 7 6 5 4 3 2 1 0 Name — — — — SR4 SR3 SR2 SR1 Default 0 0 0 0 0 0 0 0 HW Mode X X X X X X X X Bit 0/Status Register 1 (SR1). 0 = Status Register 1 interrupt not active. 1 = Status Register 1 interrupt active. Bit 1/Status Register 2 (SR2). 0 = Status Register 1 interrupt not active. 1 = Status Register 1 interrupt active. Bit 2/Status Register 3 (SR3). 0 = Status Register 1 interrupt not active. 1 = Status Register 1 interrupt active. Bit 3/Status Register 4 (SR4). 0 = Status Register 1 interrupt not active. 1 = Status Register 1 interrupt active. Bit 4/Unused. Bit 5/Unused. Bit 6/Unused. Bit 7/Unused. |
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