DS26503LN datasheet(32/123 Pages) DALLAS

32 / 123 page

DS26503 T1/E1/J1 BITS Element

32 of 123

7.3 Register Map

Table 7-2. Register Map Sorted By Address

ADDRESS

TYPE

ABBREVIATION

R/W

Test Reset Register

TSTRREG

R/W

I/O Configuration Register 1

IOCR1

R/W

I/O Configuration Register 2

IOCR2

R/W

T1 Receive Control Register 1

T1RCR1

R/W

T1 Receive Control Register 2

T1RCR2

R/W

T1 Transmit Control Register 1

T1TCR1

R/W

T1 Transmit Control Register 2

T1TCR2

R/W

T1 Common Control Register

T1CCR

R/W

Mode Configuration Register

MCREG

R/W

Transmit PLL Control Register

TPCR

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Device Identification Register

IDR

Information Register 1

INFO1

Information Register 2

INFO2

Interrupt Information Register

IIR

Status Register 1

SR1

R/W

Interrupt Mask Register 1

IMR1

Status Register 2

SR2

R/W

Interrupt Mask Register 2

IMR2

Status Register 3

SR3

R/W

Interrupt Mask Register 3

IMR3

Status Register 4

SR4

R/W

Interrupt Mask Register 4

IMR4

Information Register 3

INFO3

R/W

E1 Receive Control Register

E1RCR

R/W

E1 Transmit Control Register

E1TCR

R/W

BOC Control Register

BOCC

R/W

Loopback Control Register

LBCR

21-2F

—

Reserved

—

R/W

Line Interface Control 1

LIC1

R/W

Line Interface Control 2

LIC2

R/W

Line Interface Control 3

LIC3

R/W

Line Interface Control 4

LIC4

R/W

Transmit Line Build-Out Control

TLBC

35-3F

—

Reserved

—

R/W

Transmit Align Frame Register

TAF

R/W

Transmit Non-Align Frame Register

TNAF

R/W

Transmit Si Align Frame

TSiAF

DS26503LN Datasheet(PDF) 32 Page - Dallas Semiconductor

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