S29GL01GP datasheet(71/82 Pages) CYPRESS

71 / 82 page

Document Number: 002-00886 Rev. *B

Page 71 of 83

S29GL01GP

S29GL512P

S29GL256P

S29GL128P

Legend

X = Don’t care

RD(0) = Read data.

SA = Sector Address. Address bits Amax–A16 uniquely select any sector.

PWD = Password

PWDx = Password word0, word1, word2, and word3.

Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) =

Password Protection Mode Lock Bit.

otes

1. See Table on page 15 for description of bus operations.

2. All values are in hexadecimal.

3. All bus cycles are write cycles unless otherwise noted.

4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.

5. Address bits AMAX:A16 are don’t cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.)

6. All Lock Register bits are one-time programmable. Program state = “0” and the erase state = “1.” The Persistent Protection Mode Lock Bit

and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation aborts

and returns the device to read mode. Lock Register bits that are reserved for future use default to “1’s.” The Lock Register is shipped out

as “FFFF’s” before Lock Register Bit program execution.

7. The Exit command returns the device to reading the array.

8. If any Command Set Entry command was written, an Exit command must be issued to reset the device into read mode.

9. For PWDx, only one portion of the password can be programmed per each “A0” command.

10.Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.

11.If ACC = VHH, sector protection matches when ACC = VIH.

12.Protected State = “00h,” Unprotected State = “01h.”

13.The All PPB Erase command embeds programming of all PPB bits before erasure.

S29GL01GP Datasheet(PDF) 71 Page - Cypress Semiconductor