MP4570 datasheet(19/22 Pages) MPS

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MP4570 – 3A, 55V, SYNCHRONOUS STEP DOWN CONVERTER

MP4570 Rev. 1.01

www.MonolithicPower.com

1/4/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

The goal of compensation design is to shape the

converter transfer function for a desired loop gain.

The system crossover frequency where the

feedback loop has unity gain is important: Lower

crossover frequencies result in slower line and

load transient responses, while higher crossover

frequencies lead to system instability. Generally,

set the crossover frequency to ~0.1×fSW.

Follow these steps to design the compensation:

1. Choose R3 to set the desired crossover

frequency:

OUT

2π





Where fC is the desired crossover frequency.

2. Choose C3 to achieve the desired phase

margin. For applications with typical inductor

values, set the compensation zero (fZ1) <0.25 ×fC

to provide sufficient phase margin. C3 is then:

2π





3. C4 is required if the ESR zero of the output

capacitor is located at <0.5×fSW, or the following

relationship is valid:

2π

ESR





If this is the case, use C4 to set the pole (fP3) at

the location of the ESR zero. Determine the C4:

ESR





External Bootstrap Diode

For high duty-cycle operation (when VOUT/VIN >

65%), the time period available to the bootstrap

charging is less so the bootstrap capacitor may

not be charged sufficiently. This affects the

efficiency, even the normal operation of the part.

An external bootstrap diode from 3V-5V rail to

the BST pin can help to charge the bootstrap

capacitor and enhance the efficiency. Output

voltage is the good choice of this power supply if

it is in above range. The bootstrap diode can be

a low cost one such as IN4148 or BAT54.

Figure 2 — External Bootstrap Diode

At no-load or light-load, the converter may

operate in pulse-skipping mode in order to

maintain output-voltage regulation. Under this

condition, VSW= VOUT in most time period, so the

diode from VOUT to BST can’t charge the

bootstrap capacitor. For sufficient gate voltage

during pulse-skipping, VIN–VOUT should be no less

than 3V. For example, if the VOUT=3.3V, VIN must

exceed 3.3V+3V=6.3V to maintain sufficient

bootstrap voltage at no-load or light-load. To

meet this requirement, the EN pin can program

the input UVLO voltage to VOUT+3V

PCB Layout Guide

PCB layout is very important to stable operation.

Please follow below guidelines and use figure 3

as reference.

1) Place the ceramic input capacitor as close to

IN and GND pins as possible, especially the

small package size (0603) input bypass capacitor.

Keep the connection of input capacitor and IN pin

as short and wide as possible.

2) Place the VDD capacitor to VDD pin and GND

pin as close as possible.

3) Use large ground plane directly connect to

GND pin. Add vias near the GND pin if bottom

layer is ground plane.

4) Route SW, BST away from sensitive analog

areas such as FB.

5) Ensure all feedback connections are short and

direct. Place the feedback resistors as close to

the chip as possible.

6) Connect IN, SW, and especially GND and

exposed pad to large copper areas to cool the

chip for improved thermal performance and long-

term reliability.

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