Rev 0.90

Page 34 of 44

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PRELIMINARY

The below timing diagram and table illustrate the timing relationships for both master and slave.

P

Sr

S

VIH

1

VIH

VIL

VIL

2

8

9

8

9

SDA

SCLK

SDA

SCLK

START Condition

Repeated START Condition

S

STOP Condition START Condition

All Min and Max limits are specified over temperature and rated operating voltage with 255 Ohm resister and 550 pF output

load unless otherwise stated. Typical values are at 25°C and nominal supply voltage.

Parameter

Symbol

Standard mode

Fast mode

Fast mode plus

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

SCLK clock frequency

–

–

100

–

–

400

–

–

1000

kHz

Low period of SCLK clock

500

–

–

500

–

–

500

–

–

ns

High period of SCLK clock

260

–

–

260

–

–

260

–

–

ns

Rise time of both SCLK and SDA

–

–

120

–

–

120

–

–

120

ns

Fall time of both SCLK and SDA

30

–

70

30

–

70

30

–

70

ns

Hold time for Start condition

260

–

–

260

–

–

260

–

–

ns

Setup time for Start condition

260

–

–

260

–

–

260

–

–

ns

Data setup time

50

–

–

50

–

–

50

–

–

ns

Data hold time

0

–

–

0

–

–

0

–

–

ns

Data valid time

–

–

450

–

–

450

–

–

450

ns

Data valid acknowledge time

–

–

450

–

–

450

–

–

450

ns

Setup time for stop condition

260

–

–

260

–

–

260

–

–

ns

stop and start

500

–

–

500

–

–

500

–

–

ns